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| author | Yinghai Lu <yinghailu@gmail.com> | 2006-04-03 20:38:34 +0000 |
|---|---|---|
| committer | Yinghai Lu <yinghailu@gmail.com> | 2006-04-03 20:38:34 +0000 |
| commit | 9a791dffeae2097aa0a18f645ce07acfed41b9bc (patch) | |
| tree | 2d0359536fe3c1a0c313440b6be4ed09397dade9 /src/southbridge/nvidia | |
| parent | ffb7d8a31ae899f611235cd0a7f3579d34cd8cde (diff) | |
| download | coreboot-9a791dffeae2097aa0a18f645ce07acfed41b9bc.tar.xz | |
new cache_as_ram support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/nvidia')
| -rw-r--r-- | src/southbridge/nvidia/ck804/ck804_early_setup.c | 20 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/ck804_early_setup_car.c | 20 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/ck804_enable_rom.c | 1 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/ck804_smbus.h | 16 |
4 files changed, 49 insertions, 8 deletions
diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup.c b/src/southbridge/nvidia/ck804/ck804_early_setup.c index 7a7e467e72..bd14635541 100644 --- a/src/southbridge/nvidia/ck804/ck804_early_setup.c +++ b/src/southbridge/nvidia/ck804/ck804_early_setup.c @@ -383,3 +383,23 @@ static int ck804_early_setup_x(void) ck804_early_clear_port(); return set_ht_link_ck804(4); } + +static void hard_reset(void) +{ + set_bios_reset(); + + /* full reset */ + outb(0x0a, 0x0cf9); + outb(0x0e, 0x0cf9); +} + +static void soft_reset(void) +{ + set_bios_reset(); +#if 1 + /* link reset */ + outb(0x02, 0x0cf9); + outb(0x06, 0x0cf9); +#endif +} + diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c index bc382ca7e3..a144f1227a 100644 --- a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c +++ b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c @@ -426,3 +426,23 @@ static int ck804_early_setup_x(void) ck804_early_clear_port(ck804_num, busn, io_base); return set_ht_link_ck804(4); } + +static void hard_reset(void) +{ + set_bios_reset(); + + /* full reset */ + outb(0x0a, 0x0cf9); + outb(0x0e, 0x0cf9); +} + +static void soft_reset(void) +{ + set_bios_reset(); +#if 1 + /* link reset */ + outb(0x02, 0x0cf9); + outb(0x06, 0x0cf9); +#endif +} + diff --git a/src/southbridge/nvidia/ck804/ck804_enable_rom.c b/src/southbridge/nvidia/ck804/ck804_enable_rom.c index 48ce689358..070c09efe3 100644 --- a/src/southbridge/nvidia/ck804/ck804_enable_rom.c +++ b/src/southbridge/nvidia/ck804/ck804_enable_rom.c @@ -3,6 +3,7 @@ * by yhlu@tyan.com */ + static void ck804_enable_rom(void) { unsigned char byte; diff --git a/src/southbridge/nvidia/ck804/ck804_smbus.h b/src/southbridge/nvidia/ck804/ck804_smbus.h index 079007836f..88843585aa 100644 --- a/src/southbridge/nvidia/ck804/ck804_smbus.h +++ b/src/southbridge/nvidia/ck804/ck804_smbus.h @@ -29,14 +29,13 @@ static int smbus_wait_until_ready(unsigned smbus_io_base) unsigned char val; smbus_delay(); val = inb(smbus_io_base + SMBHSTSTAT); - if ((val & 0x1f) == 0) { - break; - } - if(loops == (SMBUS_TIMEOUT / 2)) { - outb((val & 0x1f),smbus_io_base + SMBHSTSTAT); + val &= 0x1f; + if (val == 0) { + return 0; } + outb(val,smbus_io_base + SMBHSTSTAT); } while(--loops); - return loops?0:-2; + return -2; } static int smbus_wait_until_done(unsigned smbus_io_base) @@ -49,10 +48,10 @@ static int smbus_wait_until_done(unsigned smbus_io_base) val = inb(smbus_io_base + SMBHSTSTAT); if ( (val & 0xff) != 0) { - break; + return 0; } } while(--loops); - return loops?0:-3; + return -3; } static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) { @@ -200,3 +199,4 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned } return 0; } + |