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| author | Subrata Banik <subrata.banik@intel.com> | 2018-12-31 16:23:44 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-01-03 04:31:35 +0000 |
| commit | e2c653e049d0c4db6c2712658eaa5838dac73ee9 (patch) | |
| tree | 71059f86a90fc73adf681916beb99a48281a42af /src/southbridge/nvidia | |
| parent | 12992f62c0391b2711f9f125e5f1123e08807836 (diff) | |
| download | coreboot-e2c653e049d0c4db6c2712658eaa5838dac73ee9.tar.xz | |
mb/google/hatch: Make WP_RO range align with winbond specification
This patch ensures to make memory protected range between
01C00000h - 01FFFFFFh as per winbond spi datasheet
https://www.winbond.com/resource-files/w25q256jv%20spi%20revb%2009202016.pdf
section 7.1.15
BUG=none
BRANCH=none
TEST=build for hatch.
Change-Id: I52d8dbba14bd060b48a7fe8ee009219413ef89ca
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30552
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/nvidia')
0 files changed, 0 insertions, 0 deletions