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| author | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2015-07-07 12:57:46 -0500 |
|---|---|---|
| committer | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2015-07-14 13:40:07 +0200 |
| commit | ec505ad21c923c114a16b2710a0113f657765430 (patch) | |
| tree | c3ecdb6021982e2d79220b63d40448bebe43baf2 /src/southbridge/nvidia | |
| parent | fb4233bb22602c3802da39200b85845407e0c496 (diff) | |
| download | coreboot-ec505ad21c923c114a16b2710a0113f657765430.tar.xz | |
azalia: fix up and clean up shrinkage of boilerplate code
Should fix regression in HDA verb setup on nvidia mcp55 and intel sch
southbridges. The mcp55 code could not find the mainboard's verb table
because the table was not even being compiled in. The sch boards appeared
to have the same issue.
Intel broadwell and fsp_bd82x6x seemed to have not gotten the boilerplate
shrink, so apply it to those too.
Followup-to: Ib3e09644c0ee71aacb067adaa85653d151b52078
(azalia: Shrink boilerplate)
Change-Id: If7aae69f5171db67055ffe220bdff392caaa5d9f
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10826
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/nvidia')
| -rw-r--r-- | src/southbridge/nvidia/mcp55/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/azalia.c | 11 |
2 files changed, 11 insertions, 4 deletions
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index 3e24f1c293..fb9c3fb846 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -20,6 +20,10 @@ ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +ifeq ($(CONFIG_MCP55_USE_AZA),y) +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c +endif + chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc bootblock-y += romstrap.ld diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c index 828574914c..bb4376f439 100644 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ b/src/southbridge/nvidia/mcp55/azalia.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <device/device.h> +#include <device/azalia_device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> @@ -27,6 +28,7 @@ #include <delay.h> #include "mcp55.h" +#if IS_ENABLED(CONFIG_MCP55_USE_AZA) #define HDA_ICII_REG 0x68 #define HDA_ICII_BUSY (1 << 0) #define HDA_ICII_VALID (1 << 1) @@ -86,10 +88,8 @@ no_codec: return 0; } -u32 *cim_verb_data = NULL; -u32 cim_verb_data_size = 0; -static u32 find_verb(struct device *dev, u32 viddid, u32 **verb) +static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) { int idx = 0; @@ -155,7 +155,7 @@ static int wait_for_valid(u8 *base) static void codec_init(struct device *dev, u8 *base, int addr) { u32 reg32, verb_size; - u32 *verb; + const u32 *verb; int i; printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); @@ -203,9 +203,11 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) codec_init(dev, base, i); } } +#endif static void azalia_init(struct device *dev) { +#if IS_ENABLED(CONFIG_MCP55_USE_AZA) u8 *base; u32 codec_mask, reg32; struct resource *res; @@ -253,6 +255,7 @@ static void azalia_init(struct device *dev) printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); codecs_init(dev, base, codec_mask); } +#endif } static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) |