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authorUwe Hermann <uwe@hermann-uwe.de>2010-09-25 23:47:15 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-09-25 23:47:15 +0000
commitdc3aa7abff4246bdbf5a6a397e758e4aa918a285 (patch)
treedf9e802de023a35c5999e897e34e3341a7cbf733 /src/southbridge/nvidia
parent86224f634a74bd38823c620beb647276c9c8d95c (diff)
downloadcoreboot-dc3aa7abff4246bdbf5a6a397e758e4aa918a285.tar.xz
Various Debug Port southbridge implementation fixes / cosmetics.
- Use PCI_COMMAND and PCI_COMMAND_MEMORY from pci_def.h instead of hardcoding their values. - SB600/SB700: Drop useless/unused SB600_DEVN_BASE and SB700_DEVN_BASE. - ICH7: Drop unused EHCI_CONFIG_FLAG and EHCI_PORTSC. - s/uint32_t/u32/. - Cosmetics, whitespace, coding style fixes and added code comments. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/nvidia')
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c42
1 files changed, 26 insertions, 16 deletions
diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
index 280e827cc9..f1f5c2ab11 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
@@ -21,32 +21,42 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <stdint.h>
+#include <usbdebug.h>
+#include <device/pci_def.h>
+
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
- #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
+#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
- #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
+#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
-#define EHCI_BAR_INDEX 0x10
-#define EHCI_BAR 0xFEF00000
+#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */
+#define EHCI_BAR_INDEX 0x10
#define EHCI_DEBUG_OFFSET 0x98
-#include <usbdebug.h>
-
-void set_debug_port(unsigned port)
+void set_debug_port(unsigned int port)
{
- uint32_t dword;
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), 0x74);
- dword &= ~(0xf<<12);
- dword |= (port<<12);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), 0x74, dword);
+ u32 dword;
+ device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
+ /* Write the port number to 0x74[15:12]. */
+ dword = pci_read_config32(dev, 0x74);
+ dword &= ~(0xf << 12);
+ dword |= (port << 12);
+ pci_write_config32(dev, 0x74, dword);
}
-static void mcp55_enable_usbdebug(unsigned port)
+static void mcp55_enable_usbdebug(unsigned int port)
{
+ device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
+
+ /* Mark the requested physical USB port (1-15) as the Debug Port. */
set_debug_port(port);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), EHCI_BAR_INDEX, EHCI_BAR);
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), 0x04, 0x2); // mem space enabe
-}
+ /* Set the EHCI BAR address. */
+ pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+
+ /* Enable access to the EHCI memory space registers. */
+ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+}