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| author | Myles Watson <mylesgw@gmail.com> | 2009-04-30 22:45:41 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-04-30 22:45:41 +0000 |
| commit | fa12b67771f73f0e7acf2308a13cf33b8c619884 (patch) | |
| tree | 853c5b64915c1b13749561d30bbd34c8d46f1bc4 /src/southbridge/nvidia | |
| parent | d233f363c129dae2ba5fd7ac536cf92fb4c2dd6e (diff) | |
| download | coreboot-fa12b67771f73f0e7acf2308a13cf33b8c619884.tar.xz | |
Remove warnings from compilation of the s2892 with and without CBFS.
I didn't try to remove "defined but not used" warnings because there are too
many ifdefs to be sure I wouldn't break something.
For shadowed variable declarations I renamed the inner-most variable.
The one in src/pc80/keyboard.c might need help. I didn't change the
functionality but it looks like a bug.
I boot tested it on s2892 and abuild tested it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/nvidia')
| -rw-r--r-- | src/southbridge/nvidia/ck804/ck804_lpc.c | 4 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/ck804_nic.c | 6 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/ck804_sata.c | 4 |
3 files changed, 9 insertions, 5 deletions
diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c index 1d3f6cabb5..db7c29ba84 100644 --- a/src/southbridge/nvidia/ck804/ck804_lpc.c +++ b/src/southbridge/nvidia/ck804/ck804_lpc.c @@ -171,7 +171,7 @@ static void enable_hpet(struct device *dev) pci_write_config32(dev, 0x44, 0xfed00001); hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe; - printk_debug("Enabling HPET @0x%x\n", hpet_address); + printk_debug("Enabling HPET @0x%lx\n", hpet_address); } unsigned pm_base=0; @@ -184,7 +184,7 @@ static void lpc_init(device_t dev) lpc_common_init(dev); pm_base = pci_read_config32(dev, 0x60) & 0xff00; - printk_info("%s: pm_base = %lx \n", __func__, pm_base); + printk_info("%s: pm_base = %x \n", __func__, pm_base); #if CK804_CHIP_REV==1 if (dev->bus->secondary != 1) diff --git a/src/southbridge/nvidia/ck804/ck804_nic.c b/src/southbridge/nvidia/ck804/ck804_nic.c index 82de370acc..4ad0d11a62 100644 --- a/src/southbridge/nvidia/ck804/ck804_nic.c +++ b/src/southbridge/nvidia/ck804/ck804_nic.c @@ -22,7 +22,7 @@ static void nic_init(struct device *dev) struct resource *res; res = find_resource(dev, 0x10); - base = res->base; + base = (uint8_t*)(unsigned long)res->base; #define NvRegPhyInterface 0xC0 #define PHY_RGMII 0x10000000 @@ -76,8 +76,8 @@ static void nic_init(struct device *dev) if (!eeprom_valid) { unsigned long mac_pos; mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */ - mac_l = readl(mac_pos) + nic_index; - mac_h = readl(mac_pos + 4); + mac_l = readl((uint8_t*)mac_pos) + nic_index; + mac_h = readl((uint8_t*)mac_pos + 4); } #if 1 /* Set that into NIC MMIO. */ diff --git a/src/southbridge/nvidia/ck804/ck804_sata.c b/src/southbridge/nvidia/ck804/ck804_sata.c index 7bbf900a45..e9218abf3a 100644 --- a/src/southbridge/nvidia/ck804/ck804_sata.c +++ b/src/southbridge/nvidia/ck804/ck804_sata.c @@ -11,6 +11,10 @@ #include <device/pci_ops.h> #include "ck804.h" +#ifndef CK804_SATA_RESET_FOR_ATAPI +#define CK804_SATA_RESET_FOR_ATAPI 0 +#endif + #if CK804_SATA_RESET_FOR_ATAPI static void sata_com_reset(struct device *dev, unsigned reset) // reset = 1 : reset |