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author | Eric Biederman <ebiederm@xmission.com> | 2004-10-21 10:44:08 +0000 |
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committer | Eric Biederman <ebiederm@xmission.com> | 2004-10-21 10:44:08 +0000 |
commit | dbec2d4090e40d1d8e1fd06e8d4180d3fa685d4d (patch) | |
tree | e813d3f9dea80d35cbc29d6bf35995fec0a06ab9 /src/southbridge/ricoh/rl5c476/chip.h | |
parent | f3aa4707d3bef9f529a70a204dbc648968cf7c20 (diff) | |
download | coreboot-dbec2d4090e40d1d8e1fd06e8d4180d3fa685d4d.tar.xz |
- Bump the LinuxBIOS major version
- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/ricoh/rl5c476/chip.h')
-rw-r--r-- | src/southbridge/ricoh/rl5c476/chip.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/ricoh/rl5c476/chip.h b/src/southbridge/ricoh/rl5c476/chip.h index d951a8aec1..5d7a2e3ab6 100644 --- a/src/southbridge/ricoh/rl5c476/chip.h +++ b/src/southbridge/ricoh/rl5c476/chip.h @@ -1,7 +1,7 @@ #ifndef _SOUTHBRIDGE_RICOH_RL5C476 #define _SOUTHBRIDGE_RICOH_RL5C476 -extern struct chip_control southbridge_ricoh_rl5c476_control; +extern struct chip_operations southbridge_ricoh_rl5c476_control; struct southbridge_ricoh_rl5c476_config { int num; |