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authorRonald G. Minnich <rminnich@gmail.com>2004-10-06 17:33:54 +0000
committerRonald G. Minnich <rminnich@gmail.com>2004-10-06 17:33:54 +0000
commit02fa3b2743b3f37381b6af4ee4362422b9011c8b (patch)
treec3bcc53e5ee909406558c116ac331bf05c5b561f /src/southbridge/ricoh/rl5c476/chip.h
parent4fa89208a16e1e2052fff315c76f8f3f07459571 (diff)
downloadcoreboot-02fa3b2743b3f37381b6af4ee4362422b9011c8b.tar.xz
epia-m support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/ricoh/rl5c476/chip.h')
-rw-r--r--src/southbridge/ricoh/rl5c476/chip.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/southbridge/ricoh/rl5c476/chip.h b/src/southbridge/ricoh/rl5c476/chip.h
new file mode 100644
index 0000000000..d951a8aec1
--- /dev/null
+++ b/src/southbridge/ricoh/rl5c476/chip.h
@@ -0,0 +1,10 @@
+#ifndef _SOUTHBRIDGE_RICOH_RL5C476
+#define _SOUTHBRIDGE_RICOH_RL5C476
+
+extern struct chip_control southbridge_ricoh_rl5c476_control;
+
+struct southbridge_ricoh_rl5c476_config {
+ int num;
+};
+
+#endif /* _SOUTHBRIDGE_RL5C476 */