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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-17 10:56:26 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-23 15:52:09 +0000
commita342f3937e7ce159fd170ab8cd26ba799a3bc9e4 (patch)
tree4bd4540ba11286f465272c1fbee62dbf5f9789f8 /src/southbridge/ricoh
parent9856892297ad997f586a1b4dd0a494f3764a0ce2 (diff)
downloadcoreboot-a342f3937e7ce159fd170ab8cd26ba799a3bc9e4.tar.xz
src: Remove unneeded whitespace
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/ricoh')
-rw-r--r--src/southbridge/ricoh/rl5c476/rl5c476.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c
index bdbcba7053..786a510c8b 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.c
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.c
@@ -166,7 +166,7 @@ static void rl5c476_read_resources(struct device *dev)
/* For CF socket we need an extra memory window for
* the control structure of the CF itself
*/
- if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
+ if (enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)) {
/* fake index as it isn't in PCI config space */
resource = new_resource(dev, 1);
resource->flags |= IORESOURCE_MEM;
@@ -181,9 +181,9 @@ static void rl5c476_set_resources(struct device *dev)
{
struct resource *resource;
printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev));
- if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
+ if (enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)) {
resource = find_resource(dev,1);
- if ( !(resource->flags & IORESOURCE_STORED) ){
+ if (!(resource->flags & IORESOURCE_STORED)) {
resource->flags |= IORESOURCE_STORED;
printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base);
cf_base = resource->base;