diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-31 19:22:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:22:46 +0200 |
| commit | ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 (patch) | |
| tree | 9f7e4416b63e26ee3f4df6f9a61ab55f377bcb5f /src/southbridge/ricoh | |
| parent | 2e4d80687dd79890c7c9edad8dbaf6e89edf2afc (diff) | |
| download | coreboot-ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1.tar.xz | |
src/southbridge: Code formating
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/ricoh')
| -rw-r--r-- | src/southbridge/ricoh/rl5c476/rl5c476.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 083d0641c7..8284ec810e 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -166,7 +166,7 @@ static void rl5c476_read_resources(device_t dev) /* For CF socket we need an extra memory window for * the control structure of the CF itself */ - if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ + if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ /* fake index as it isn't in PCI config space */ resource = new_resource(dev, 1); resource->flags |= IORESOURCE_MEM; @@ -181,9 +181,9 @@ static void rl5c476_set_resources(device_t dev) { struct resource *resource; printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev)); - if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ + if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ resource = find_resource(dev,1); - if( !(resource->flags & IORESOURCE_STORED) ){ + if ( !(resource->flags & IORESOURCE_STORED) ){ resource->flags |= IORESOURCE_STORED ; printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base); cf_base = resource->base; |