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| author | Sven Schnelle <svens@stackframe.org> | 2011-04-20 08:58:38 +0000 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2011-04-20 08:58:38 +0000 |
| commit | 81725b2effe9269e5079c6043077ba516e72aa82 (patch) | |
| tree | 36d93d3eaa95598bef4c64e6595aa454993cfa5e /src/southbridge/ti/pci1x2x/chip.h | |
| parent | 5c72a8752bb5ce1c3b1bfb77c08039c71c2113ef (diff) | |
| download | coreboot-81725b2effe9269e5079c6043077ba516e72aa82.tar.xz | |
pci1x2x: remove latency/bridge control/cacheline size settings
Those settings should be handled by the generic PCI/Cardbus code,
and not by the driver itself.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/ti/pci1x2x/chip.h')
| -rw-r--r-- | src/southbridge/ti/pci1x2x/chip.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/southbridge/ti/pci1x2x/chip.h b/src/southbridge/ti/pci1x2x/chip.h index b40194e328..4c3676153d 100644 --- a/src/southbridge/ti/pci1x2x/chip.h +++ b/src/southbridge/ti/pci1x2x/chip.h @@ -6,8 +6,5 @@ extern struct chip_operations southbridge_ti_pci1x2x_ops; struct southbridge_ti_pci1x2x_config { int scr; int mrr; - int clsr; - int cltr; - int bcr; }; #endif |