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| author | Sven Schnelle <svens@stackframe.org> | 2011-04-20 08:57:53 +0000 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2011-04-20 08:57:53 +0000 |
| commit | baec0346b028d59c4ec226961d977bec0c57ed7e (patch) | |
| tree | f1ee11002f329595b1838667d9b3aac5aa617cf7 /src/southbridge/ti/pci1x2x/chip.h | |
| parent | b297b4901a5e7dd0aa037b184329a0e96722149e (diff) | |
| download | coreboot-baec0346b028d59c4ec226961d977bec0c57ed7e.tar.xz | |
pci1x2x: use devicetree register configuration
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/ti/pci1x2x/chip.h')
| -rw-r--r-- | src/southbridge/ti/pci1x2x/chip.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/southbridge/ti/pci1x2x/chip.h b/src/southbridge/ti/pci1x2x/chip.h new file mode 100644 index 0000000000..b40194e328 --- /dev/null +++ b/src/southbridge/ti/pci1x2x/chip.h @@ -0,0 +1,13 @@ +#ifndef SOUTHBRIDGE_TI_PCI1X2X_H +#define SOUTHBRIDGE_TI_PCI1X2X_H + +extern struct chip_operations southbridge_ti_pci1x2x_ops; + +struct southbridge_ti_pci1x2x_config { + int scr; + int mrr; + int clsr; + int cltr; + int bcr; +}; +#endif |