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authorAaron Durbin <adurbin@chromium.org>2012-12-19 14:38:01 -0600
committerRonald G. Minnich <rminnich@gmail.com>2013-03-14 20:18:57 +0100
commit6f561afa4a635958dedf20ffda9a40c6f5e5699e (patch)
tree5caf818c7f05c5caa4885e0c6604492e4e5ad907 /src/southbridge/ti/pci1x2x
parent26e7dd703dea8dce30829d8bb73c1f27a2178d72 (diff)
downloadcoreboot-6f561afa4a635958dedf20ffda9a40c6f5e5699e.tar.xz
lynxpoint: lpc resource reservations
This commit updates the Lynx Point resource reservations before the coreboot allocator assigns resources. There is no need to mark anything as subtractive decode because there are no devices/buses linked to the LPC device. The I/O range reservations consists of claiming the first 4KiB of I/O space. The PMBASE, GPIOBASE, and LPC generic I/O decode ranges are checked against the default claimed range. If those ranges overlap or fall outside of the default range then those resources are added. The MMIO range reservations consist of claiming everything from the I/O APIC to 4GiB. The RCBA and the LPC Generic Memory range register are then conditionally added if they fall outside of the default MMIO range. Change-Id: I0f560a03814a2b15961fdbe61e4164cd54cff7a5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2682 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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