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authorPatrick Rudolph <siro@das-labor.org>2015-06-22 19:32:53 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-06-23 01:50:16 +0200
commit8c639359ea6dcb0eb445a37c1c276652b34ff437 (patch)
tree527e84989e5525ad968c0c6e53876d7c31b65e48 /src/southbridge/ti
parent6762a8b85e631c9076990021ac2392c5efcbda21 (diff)
downloadcoreboot-8c639359ea6dcb0eb445a37c1c276652b34ff437.tar.xz
ddr3: Fix SPD CRC calculation
Use the correct SPD size for crc calculation. sizeof(*spd) returns 4 while sizeof(spd_raw_data) returns the expected value of 256. Fixes erroneous printing of "ERROR: SPD CRC failed!!!" in raminit log. Verified by testing this code on Intel IvyBridge and Gigabyte GA-B75M-D3H. Change-Id: Iba305c69debd64fa921e08e00ec0a3531c80f56f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10629 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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