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| author | Florian Zumbiehl <florz@florz.de> | 2011-11-01 20:18:30 +0100 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-11-07 19:17:24 +0100 |
| commit | 1e1e8593bc9218c62dc187ce965020045ab385ea (patch) | |
| tree | 5be431b360fabb20aa5adaa8a2b4f59c6112bd37 /src/southbridge/via/k8t890/dram.c | |
| parent | 7b1d295f62be4c4d59ea8d1ac18e8ef0bedbca6e (diff) | |
| download | coreboot-1e1e8593bc9218c62dc187ce965020045ab385ea.tar.xz | |
factor out common config for k8x8xx's dram_enable() and vt8237r_cfg()
Instead of writing to config registers in k8x8xx's dram_enable()
and reading those back in vt8237r_cfg(), factor out generation of
the values and reuse that in both places.
Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/378
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/via/k8t890/dram.c')
| -rw-r--r-- | src/southbridge/via/k8t890/dram.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 9b43a5e57f..294e3871dd 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -30,14 +30,15 @@ static void dram_enable(struct device *dev) { - msr_t msr; u16 reg; + struct k8x8xx_vt8237_mirrored_regs mregs; + k8x8xx_vt8237_mirrored_regs_fill(&mregs); /* * Enable Lowest Interrupt arbitration for APIC, enable NB APIC * decoding, MSI support, no SMRAM, compatible SMM. */ - pci_write_config8(dev, 0x86, 0x19); + pci_write_config8(dev, 0x86, mregs.smm_apic_decoding); /* * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if @@ -48,23 +49,22 @@ static void dram_enable(struct device *dev) /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for * C0000-C3FFF etc. */ - pci_write_config8(dev, 0x80, 0xff); + pci_write_config8(dev, 0x80, mregs.rom_shadow_ctrl_pg_c); /* For page D0000-DFFFF */ - pci_write_config8(dev, 0x81, 0xff); + pci_write_config8(dev, 0x81, mregs.rom_shadow_ctrl_pg_d); /* For page E0000-EFFFF */ - pci_write_config8(dev, 0x82, 0xff); - pci_write_config8(dev, 0x83, 0x30); + pci_write_config8(dev, 0x82, mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding); + pci_write_config8(dev, 0x83, mregs.rom_shadow_ctrl_pg_f_memhole); - msr = rdmsr(TOP_MEM); reg = pci_read_config16(dev, 0x84); reg &= 0xf; - pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg); + pci_write_config16(dev, 0x84, mregs.low_top_address | reg); reg = pci_read_config16(dev, 0x88); reg &= 0xf800; /* The Address Next to the Last Valid DRAM Address */ - pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); + pci_write_config16(dev, 0x88, reg | mregs.shadow_mem_ctrl); print_debug(" VIA_X_3 device dump:\n"); dump_south(dev); |