diff options
author | Stefan Reinauer <reinauer@chromium.org> | 2015-01-05 13:01:01 -0800 |
---|---|---|
committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-01-06 20:15:20 +0100 |
commit | 5ab52ddc3dc289267b603c0a348c461d336aeaf5 (patch) | |
tree | 7ebe9f17e224426ad570028ec12188e165617517 /src/southbridge/via/k8t890 | |
parent | 65b72ab55d7dff1f13cdf495d345e04e634b97ac (diff) | |
download | coreboot-5ab52ddc3dc289267b603c0a348c461d336aeaf5.tar.xz |
southbridge: Drop print_ implementation from non-romcc boards
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the southbridge code to use printk() on all non-ROMCC
boards.
Change-Id: I312406257e66bbdc3940e206b5256460559a2c98
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8110
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/via/k8t890')
-rw-r--r-- | src/southbridge/via/k8t890/bridge.c | 2 | ||||
-rw-r--r-- | src/southbridge/via/k8t890/ctrl.c | 8 | ||||
-rw-r--r-- | src/southbridge/via/k8t890/dram.c | 2 | ||||
-rw-r--r-- | src/southbridge/via/k8t890/early_car.c | 25 | ||||
-rw-r--r-- | src/southbridge/via/k8t890/error.c | 6 | ||||
-rw-r--r-- | src/southbridge/via/k8t890/host.c | 2 | ||||
-rw-r--r-- | src/southbridge/via/k8t890/host_ctrl.c | 2 |
7 files changed, 22 insertions, 25 deletions
diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 2da31f4be7..fdf5b9d746 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -26,7 +26,7 @@ static void bridge_enable(struct device *dev) { u8 tmp; - print_debug("B188 device dump\n"); + printk(BIOS_DEBUG, "B188 device dump\n"); /* VIA recommends this, sorry no known info. */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index a918f01640..782c547dfb 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -152,7 +152,7 @@ static void vt8237r_vlink_init(struct device *dev) static void ctrl_init(struct device *dev) { - print_debug("K8x8xx: Initializing V-Link to VT8237R sb: "); + printk(BIOS_DEBUG, "K8x8xx: Initializing V-Link to VT8237R sb: "); /* TODO: Fix some ordering issue for V-link set Rx77[6] and PCI1_Rx4F[0] should to 1 */ @@ -172,11 +172,11 @@ static void ctrl_init(struct device *dev) vt8237r_vlink_init(dev); k8x8xx_vt8237r_cfg(dev, devsb); } else { - print_debug("VT8237R LPC not found !\n"); + printk(BIOS_DEBUG, "VT8237R LPC not found !\n"); return; } - print_debug(" Done\n"); - print_debug(" VIA_X_7 device dump:\n"); + printk(BIOS_DEBUG, " Done\n"); + printk(BIOS_DEBUG, " VIA_X_7 device dump:\n"); dump_south(dev); } diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 07a34b73fb..04184b76a3 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -66,7 +66,7 @@ static void dram_enable(struct device *dev) /* The Address Next to the Last Valid DRAM Address */ pci_write_config16(dev, 0x88, reg | mregs.shadow_mem_ctrl); - print_debug(" VIA_X_3 device dump:\n"); + printk(BIOS_DEBUG, " VIA_X_3 device dump:\n"); dump_south(dev); } diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index d7049ae3ba..7eba967a73 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -80,23 +80,23 @@ u8 k8t890_early_setup_ht(void) } #if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800 - print_debug("K8M800 found at LDT "); + printk(BIOS_DEBUG, "K8M800 found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 - print_debug("K8T800 found at LDT "); + printk(BIOS_DEBUG, "K8T800 found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD - print_debug("K8T800_OLD found at LDT "); + printk(BIOS_DEBUG, "K8T800_OLD found at LDT "); pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00); pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50); #elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800PRO - print_debug("K8T800 Pro found at LDT "); + printk(BIOS_DEBUG, "K8T800 Pro found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 - print_debug("K8M890 found at LDT "); + printk(BIOS_DEBUG, "K8M890 found at LDT "); /* K8M890 fix HT delay */ pci_write_config8(PCI_DEV(0, 0x0, 2), 0xab, 0x22); #elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890 - print_debug("K8T890 found at LDT "); + printk(BIOS_DEBUG, "K8T890 found at LDT "); #endif - print_debug_hex8(ldtnr); + printk(BIOS_DEBUG, "%02x", ldtnr); /* get the maximum widths for both sides */ cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7; @@ -105,8 +105,7 @@ u8 k8t890_early_setup_ht(void) vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) >> 4) & 0x7; width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in); - print_debug(" Agreed on width: "); - print_debug_hex8(width); + printk(BIOS_DEBUG, " Agreed on width: %02x", width); awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7); @@ -117,12 +116,10 @@ u8 k8t890_early_setup_ht(void) /* Get programmed HT freq at base 0x89 */ cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf; - print_debug(" CPU programmed to HT freq: "); - print_debug_hex8(cldtfreq); + printk(BIOS_DEBUG, " CPU programmed to HT freq: %02x", cldtfreq); - print_debug(" VIA HT caps: "); vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), K8X8XX_HT_CFG_BASE + 0xe); - print_debug_hex16(vldtcaps); + printk(BIOS_DEBUG, " VIA HT caps: %04x", vldtcaps); if (!(vldtcaps & (1 << cldtfreq ))) { die("Chipset does not support desired HT frequency\n"); @@ -130,7 +127,7 @@ u8 k8t890_early_setup_ht(void) afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd); pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd, cldtfreq); - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); /* no reset needed */ if ((width == awidth) && (afreq == cldtfreq)) { diff --git a/src/southbridge/via/k8t890/error.c b/src/southbridge/via/k8t890/error.c index 087028895d..2c1b5b681e 100644 --- a/src/southbridge/via/k8t890/error.c +++ b/src/southbridge/via/k8t890/error.c @@ -26,7 +26,7 @@ static void error_enable(struct device *dev) { - print_debug(" K8x8xx: Enabling NB error reporting: "); + printk(BIOS_DEBUG, " K8x8xx: Enabling NB error reporting: "); /* * bit0 - Enable V-link parity error reporting in 0x50 bit0 (RWC) * bit6 - Parity Error/SERR# Report Through V-Link to SB @@ -34,10 +34,10 @@ static void error_enable(struct device *dev) */ pci_write_config8(dev, 0x58, 0x81); - print_debug("Done\n"); + printk(BIOS_DEBUG, "Done\n"); /* TODO: enable AGP errors reporting on K8M890 */ - print_debug(" VIA_X_1 device dump:\n"); + printk(BIOS_DEBUG, " VIA_X_1 device dump:\n"); dump_south(dev); } diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index aa1b748339..878ee9a6f9 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -60,7 +60,7 @@ static void host_enable(struct device *dev) /* Multiple function control */ pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01); - print_debug(" VIA_X_0 device dump:\n"); + printk(BIOS_DEBUG, " VIA_X_0 device dump:\n"); dump_south(dev); } diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c index 74351bc3d0..2f4bca7cf1 100644 --- a/src/southbridge/via/k8t890/host_ctrl.c +++ b/src/southbridge/via/k8t890/host_ctrl.c @@ -84,7 +84,7 @@ static void host_ctrl_enable_k8t8xx(struct device *dev) writeback(dev, 0xc4, 0x50); writeback(dev, 0xc5, 0x50); - print_debug(" VIA_X_2 device dump:\n"); + printk(BIOS_DEBUG, " VIA_X_2 device dump:\n"); dump_south(dev); } |