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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-09-04 13:26:11 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-09-11 07:18:02 +0200 |
| commit | bc90e15d3f8e841ccf229fca5d7df99436ff4bdb (patch) | |
| tree | bbbd4f2904b42d201d7e2fbccea5bfcbeeeed166 /src/southbridge/via/k8t890 | |
| parent | c04afd6433cd53acdc727ad760cde9c40090030b (diff) | |
| download | coreboot-bc90e15d3f8e841ccf229fca5d7df99436ff4bdb.tar.xz | |
CBMEM: Backup top_of_ram instead of cbmem_toc
AMD northbridges have a complex way to resolve top_of_ram.
Once it is resolved, it is stored in NVRAM to be used on resume.
TODO: Redesign these get_top_of_ram() functions from scratch.
Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge/via/k8t890')
| -rw-r--r-- | src/southbridge/via/k8t890/early_car.c | 9 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/host_ctrl.c | 9 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/k8t890.h | 2 |
3 files changed, 10 insertions, 10 deletions
diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index 000a5322ba..d7049ae3ba 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -183,6 +183,11 @@ static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -struct cbmem_entry *get_cbmem_toc(void) { - return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +#if CONFIG_HAVE_ACPI_RESUME +unsigned long get_top_of_ram(void) +{ + if (!acpi_is_wakeup_early()) + return 0; + return (unsigned long) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); } +#endif diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c index 151a2287ec..74351bc3d0 100644 --- a/src/southbridge/via/k8t890/host_ctrl.c +++ b/src/southbridge/via/k8t890/host_ctrl.c @@ -113,13 +113,8 @@ static void host_ctrl_enable_k8m8xx(struct device *dev) { pci_write_config8(dev, 0xa6, 0x83); } -#if 0 -struct cbmem_entry *get_cbmem_toc(void) { - return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); -} -#endif -void set_cbmem_toc(struct cbmem_entry *toc) { - outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +void backup_top_of_ram(uint64_t ramtop) { + outl((u32) ramtop, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h index f0d0fe0b83..7f83ffad3f 100644 --- a/src/southbridge/via/k8t890/k8t890.h +++ b/src/southbridge/via/k8t890/k8t890.h @@ -31,7 +31,7 @@ /* The 256 bytes of NVRAM for S3 storage, 256B aligned */ #define K8T890_NVRAM_IO_BASE 0xf00 -#define K8T890_NVRAM_CBMEM_TOC 0xfc +#define K8T890_NVRAM_TOP_OF_RAM 0xfc #define K8T890_MMCONFIG_MBAR 0x61 #define K8T890_MULTIPLE_FN_EN 0x4f |