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| author | Stefan Reinauer <reinauer@chromium.org> | 2014-12-17 13:31:54 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2014-12-18 02:13:53 +0100 |
| commit | e4c73bb5baac96ca49c5dea1916dfcfbd1af2e26 (patch) | |
| tree | fd8516b36fac98cec70b45724c2324cc2329ac52 /src/southbridge/via/vt8231/chip.h | |
| parent | 5878bbd935c8cbd7c6d25ef72a5460f3262119e7 (diff) | |
| download | coreboot-e4c73bb5baac96ca49c5dea1916dfcfbd1af2e26.tar.xz | |
Drop VIA Epia mainboard
.. and also drop the northbridge and southbridge used by the board.
This is one of the last boards to not use ROMCC for romstage. Let's
get rid of it.
Change-Id: I0a864b2c4ce3eeb7d3e199944eedef0cd71a85e6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7853
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge/via/vt8231/chip.h')
| -rw-r--r-- | src/southbridge/via/vt8231/chip.h | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/src/southbridge/via/vt8231/chip.h b/src/southbridge/via/vt8231/chip.h deleted file mode 100644 index e858ff5086..0000000000 --- a/src/southbridge/via/vt8231/chip.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _SOUTHBRIDGE_VIA_VT8231 -#define _SOUTHBRIDGE_VIA_VT8231 - -struct southbridge_via_vt8231_config { - /* enables of Non-PCI devices */ - int enable_native_ide; - int enable_com_ports; - int enable_keyboard; - /* currently not parsed but needed by densitron dpx114 */ - int enable_usb; - int enable_nvram; -}; - -#endif /* _SOUTHBRIDGE_VIA_VT8231 */ |