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authorBen Hewson <ben@hewson-venieri.com>2007-05-04 19:43:57 +0000
committerRonald G. Minnich <rminnich@gmail.com>2007-05-04 19:43:57 +0000
commitb93f9cadb2a13f53cf8a6c405b2fd623898f418c (patch)
treeee7d2bf522f12646ac64f3bedeceac36a702fcd3 /src/southbridge/via/vt8231
parent08da4f1fce68748c2aea8ef5ff4109ea6d3f0d82 (diff)
downloadcoreboot-b93f9cadb2a13f53cf8a6c405b2fd623898f418c.tar.xz
patch to fix the IDE configuration on EPIA boards. At some point this
broke and stopped FILO from being able to boot. The fix is a simple one line change plus a comment to src/mainboard/via/epia/auto.c to write to the IDE configuration register 0x42 . This has always been done here, however at some point something broke it. The same register was also being set correctly in ide_init(), however for some reason this does not work. Possibly the register needs to be set before the IDE peripheral is enabled or maybe it is a timing issue. The section of code in ide_init() ( src/southbridge/via/vt8231/vt8231_ide.c ) that does write to register 0x42 has been commented out as it is superfluous and I have added a comment to indicate the reason, should someone at a future date wonder why. I have also changed the default COM speed from 19200 to 115200 in src/mainboard/via/epia/Options.lb There has been mention before about the EPIA board not being able to use 115200 but I have seen no such problems with my board. Signed-off-by: Ben Hewson <ben@hewson-venieri.com> This patch worked for me and allowed me to boot Debian kernel 2.5.16-4-486 on an epia 800 mhz system. It is able to consistently get through the initialization and start init now. However, after that it crashes at various points in the boot process. Acked-by: Alex Mauer <hawke@hawkesnest.net> Note from comitter: I am commiting this, although: 1. it's not the exact right way to fix it up, the chip.h for the sb should change 2. Alex reports problems, which are almost certainly memory issues. But it is as close as we've gotten. I can't test it. Ron Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via/vt8231')
-rw-r--r--src/southbridge/via/vt8231/vt8231_ide.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/southbridge/via/vt8231/vt8231_ide.c b/src/southbridge/via/vt8231/vt8231_ide.c
index 9f06176cc5..dd0e1bb419 100644
--- a/src/southbridge/via/vt8231/vt8231_ide.c
+++ b/src/southbridge/via/vt8231/vt8231_ide.c
@@ -14,7 +14,12 @@ static void ide_init(struct device *dev)
if (!conf->enable_native_ide) {
// Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
// interrupts. Using PCI ints confuses linux for some reason.
-
+ /* Setting reg 0x42 here does not work. It is set in mainboard/auto.c
+ * It probably can only be changed while the IDE is disabled
+ * or it is possibly a timing issue. Ben Hewson 29 Apr 2007.
+ */
+
+ /*
printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__);
enables = pci_read_config8(dev, 0x42);
printk_debug("enables in reg 0x42 0x%x\n", enables);
@@ -22,6 +27,7 @@ static void ide_init(struct device *dev)
pci_write_config8(dev, 0x42, enables);
enables = pci_read_config8(dev, 0x42);
printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
+ */
}
enables = pci_read_config8(dev, 0x40);