Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 87 insertions, 87 deletions

diff --git a/src/southbridge/via/vt8235/vt8235.c b/src/southbridge/via/vt8235/vt8235.c
index 747c2157f1..4fa2784661 100644
--- a/src/southbridge/via/vt8235/vt8235.c
+++ b/src/southbridge/via/vt8235/vt8235.c
@@ -12,7 +12,7 @@ static void keyboard_on(struct device *dev)
 	u8 regval;
 
 	regval = pci_read_config8(dev, 0x51);
-	regval |= 0x05; 
+	regval |= 0x05;
 	regval &= 0xfd;
 	pci_write_config8(dev, 0x51, regval);
 
@@ -23,7 +23,7 @@ static void keyboard_on(struct device *dev)
 void dump_south(device_t dev0)
 {
 	int i,j;
-	
+
 	for(i = 0; i < 256; i += 16) {
 		printk(BIOS_DEBUG, "0x%x: ", i);
 		for(j = 0; j < 16; j++) {
@@ -51,10 +51,10 @@ static void vt8235_enable(struct device *dev)
 	model = pci_read_config16(dev,0x2);
 
 	printk(BIOS_DEBUG, "In vt8235_enable %04x %04x.\n",vendor,model);
-	
+
 	/* If this is not the southbridge itself just return.
 	 * This is necessary because USB devices are slot 10, whereas this
-	 * device is slot 11 therefore usb devices get called first during 
+	 * device is slot 11 therefore usb devices get called first during
 	 * the bus scan. We don't want to wait until we could do dev->init
 	 * because that's too late.
 	 */
@@ -69,13 +69,13 @@ static void vt8235_enable(struct device *dev)
 
 	/* enable RTC and ethernet */
 	regval = pci_read_config8(dev, 0x51);
-	regval |= 0x18; 
+	regval |= 0x18;
 	pci_write_config8(dev, 0x51, regval);
 
 	/* turn on keyboard */
 	keyboard_on(dev);
 
-	/* enable USB 1.1 & USB 2.0 - redundant really since we've 
+	/* enable USB 1.1 & USB 2.0 - redundant really since we've
 	 * already been there - see note above
 	 */
    	regval = pci_read_config8(dev, 0x50);
diff --git a/src/southbridge/via/vt8235/vt8235_early_serial.c b/src/southbridge/via/vt8235/vt8235_early_serial.c
index 7823172485..11f98fae39 100644
--- a/src/southbridge/via/vt8235/vt8235_early_serial.c
+++ b/src/southbridge/via/vt8235/vt8235_early_serial.c
@@ -8,25 +8,25 @@
 #define SIO_BASE 0x3f0
 #define SIO_DATA  SIO_BASE+1
 
-static void vt8235_writepnpaddr(uint8_t val) 
+static void vt8235_writepnpaddr(uint8_t val)
 {
 	outb(val, 0x2e);
 	outb(val, 0xeb);
 }
 
-static void vt8235_writepnpdata(uint8_t val) 
+static void vt8235_writepnpdata(uint8_t val)
 {
 	outb(val, 0x2f);
 	outb(val, 0xeb);
 }
 
 
-static void vt8235_writesiobyte(uint16_t reg, uint8_t val) 
+static void vt8235_writesiobyte(uint16_t reg, uint8_t val)
 {
 	outb(val, reg);
 }
 
-static void vt8235_writesioword(uint16_t reg, uint16_t val) 
+static void vt8235_writesioword(uint16_t reg, uint16_t val)
 {
 	outw(val, reg);
 }
@@ -36,12 +36,12 @@ static void vt8235_writesioword(uint16_t reg, uint16_t val)
    mainboard
  */
 
-static void enable_vt8235_serial(void) 
+static void enable_vt8235_serial(void)
 {
 	// turn on pnp
 	vt8235_writepnpaddr(0x87);
 	vt8235_writepnpaddr(0x87);
-	// now go ahead and set up com1. 
+	// now go ahead and set up com1.
 	// set address
 	vt8235_writepnpaddr(0x7);
 	vt8235_writepnpdata(0x2);
diff --git a/src/southbridge/via/vt8235/vt8235_early_smbus.c b/src/southbridge/via/vt8235/vt8235_early_smbus.c
index db403eb5fb..1876461a3d 100644
--- a/src/southbridge/via/vt8235/vt8235_early_smbus.c
+++ b/src/southbridge/via/vt8235/vt8235_early_smbus.c
@@ -12,7 +12,7 @@
 #define SMBTRNSADD 0x9
 #define SMBSLVDATA 0xa
 #define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL  0xf 
+#define SMBUS_PIN_CTL  0xf
 
 /* Define register settings */
 #define HOST_RESET 0xff
@@ -34,17 +34,17 @@ static void enable_smbus(void)
 	/* Power management controller */
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
 				PCI_DEVICE_ID_VIA_8235), 0);
-	
+
 	if (dev == PCI_DEV_INVALID) {
 		die("SMBUS controller not found\n");
-	}		
+	}
 
 	// set IO base address to SMBUS_IO_BASE
 	pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
-	
-	// Enable SMBus 
+
+	// Enable SMBus
 	pci_write_config8(dev, 0xd2, (0x4 << 1) | 1);
-	
+
 	/* make it work for I/O ...
 	 */
 	pci_write_config16(dev, 4, 1);
@@ -55,13 +55,13 @@ static void enable_smbus(void)
 	for(i = 0 ; i < 5000 ; i++)
 		outb(0x80,0x80);
 
-	/* 
+	/*
 	 * The VT1211 serial port needs 48 mhz clock, on power up it is getting
 	 *  only 24 mhz, there is some mysterious device on the smbus that can
 	 *  fix this...this code below does it.
 	 *  */
-	outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT); 
-	outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0); 
+	outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT);
+	outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0);
 	outb(0x83, SMBUS_IO_BASE+SMBHSTCMD);
 	outb(CLOCK_SLAVE_ADDRESS<<1 , SMBUS_IO_BASE+SMBXMITADD);
 	outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL);
@@ -92,7 +92,7 @@ static int smbus_wait_until_ready(void)
 			print_debug_hex8(c);
 			print_debug("\n");
 			c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-			/* nop */ 
+			/* nop */
 		}
 
 	} while(--loops);
@@ -105,13 +105,13 @@ void smbus_reset(void)
 	outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
 	outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
 	outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
-	
+
 	smbus_wait_until_ready();
 	print_debug("After reset status ");
 	print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
 	print_debug("\n");
 }
-  
+
 
 
 static int smbus_wait_until_done(void)
@@ -121,11 +121,11 @@ static int smbus_wait_until_done(void)
 	loops = SMBUS_TIMEOUT;
 	do {
 		smbus_delay();
-		
+
 		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
 		if (byte & 1)
 			break;
-		
+
 	} while(--loops);
 	return loops?0:-1;
 }
@@ -156,46 +156,46 @@ static void smbus_print_error(unsigned char host_status_register)
 
 /* SMBus routines borrowed from VIA's Trident Driver */
 /* this works, so I am not going to touch it for now -- rgm */
-static unsigned char smbus_read_byte(unsigned char devAdr, 
-				unsigned char bIndex) 
+static unsigned char smbus_read_byte(unsigned char devAdr,
+				unsigned char bIndex)
 {
 	unsigned short i;
 	unsigned char  bData;
 	unsigned char  sts = 0;
-	
+
 	/* clear host status */
 	outb(0xff, SMBUS_IO_BASE);
-	
+
 	/* check SMBUS ready */
 	for ( i = 0; i < 0xFFFF; i++ )
 		if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 )
 			break;
-	
+
 	/* set host command */
 	outb(bIndex, SMBUS_IO_BASE+3);
-	
+
 	/* set slave address */
 	outb(devAdr | 0x01, SMBUS_IO_BASE+4);
-	
+
 	/* start */
 	outb(0x48, SMBUS_IO_BASE+2);
-	
+
 	/* SMBUS Wait Ready */
 	for ( i = 0; i < 0xFFFF; i++ )
 		if ( ((sts = (inb(SMBUS_IO_BASE) & 0x1f)) & 0x01) == 0 )
 			break;
-	
+
 	if ((sts & ~3) != 0) {
 		smbus_print_error(sts);
 		return 0;
 	}
 	bData=inb(SMBUS_IO_BASE+5);
-	
+
 	return bData;
-	
+
 }
 
-/* for reference, here is the fancier version which we will use at some 
+/* for reference, here is the fancier version which we will use at some
  * point
  */
 # if 0
@@ -203,11 +203,11 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
 {
 	unsigned char host_status_register;
 	unsigned char byte;
-	
+
 	reset();
-	
+
 	smbus_wait_until_ready();
-	
+
 	/* setup transaction */
 	/* disable interrupts */
 	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
@@ -218,29 +218,29 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
 	/* set up for a byte data read */
 	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
 		SMBUS_IO_BASE + SMBHSTCTL);
-	
+
 	/* clear any lingering errors, so the transaction will run */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-	
+
 	/* clear the data byte...*/
 	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
-	
+
 	/* start the command */
 	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
 		SMBUS_IO_BASE + SMBHSTCTL);
-	
+
 	/* poll for transaction completion */
 	smbus_wait_until_done();
-	
+
 	host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-	
+
 	/* Ignore the In Use Status... */
 	host_status_register &= ~(1 << 6);
-	
+
 	/* read results of transaction */
 	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
 	smbus_print_error(byte);
-	
+
 	*result = byte;
 	return host_status_register != 0x02;
 }
diff --git a/src/southbridge/via/vt8235/vt8235_ide.c b/src/southbridge/via/vt8235/vt8235_ide.c
index ec22f9053b..961f860fed 100644
--- a/src/southbridge/via/vt8235/vt8235_ide.c
+++ b/src/southbridge/via/vt8235/vt8235_ide.c
@@ -28,69 +28,69 @@ static void ide_init(struct device *dev)
 		printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n",
 				enables);
 	/* } */
-	
+
 	enables = pci_read_config8(dev, 0x40);
 	printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables);
 	enables |= 3;
 	pci_write_config8(dev, 0x40, enables);
 	enables = pci_read_config8(dev, 0x40);
 	printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
-	
+
 	// Enable prefetch buffers
 	enables = pci_read_config8(dev, 0x41);
 	enables |= 0xf0;
 	pci_write_config8(dev, 0x41, enables);
-	
+
 	// Lower thresholds (cause award does it)
 	enables = pci_read_config8(dev, 0x43);
 	enables &= ~0x0f;
 	enables |=  0x05;
 	pci_write_config8(dev, 0x43, enables);
-	
+
 	// PIO read prefetch counter (cause award does it)
 	pci_write_config8(dev, 0x44, 0x18);
-	
+
 	// Use memory read multiple
 	pci_write_config8(dev, 0x45, 0x1c);
-	
-	// address decoding. 
+
+	// address decoding.
 	// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
-	// kevinh@ispiri.com - the standard linux drivers seem ass slow when 
+	// kevinh@ispiri.com - the standard linux drivers seem ass slow when
 	// used in native mode - I've changed back to classic
 	enables = pci_read_config8(dev, 0x9);
 	printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables);
-	// by the book, set the low-order nibble to 0xa. 
+	// by the book, set the low-order nibble to 0xa.
 	if (conf->enable_native_ide) {
 		enables &= ~0xf;
-		// cf/cg silicon needs an 'f' here. 
+		// cf/cg silicon needs an 'f' here.
 		enables |= 0xf;
 	} else {
 		enables &= ~0x5;
 	}
-	
+
 	pci_write_config8(dev, 0x9, enables);
 	enables = pci_read_config8(dev, 0x9);
 	printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables);
-	
-	// standard bios sets master bit. 
+
+	// standard bios sets master bit.
 	enables = pci_read_config8(dev, 0x4);
 	printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables);
 	enables |= 7;
-	
+
 	// No need for stepping - kevinh@ispiri.com
 	enables &= ~0x80;
-	
+
 	pci_write_config8(dev, 0x4, enables);
 	enables = pci_read_config8(dev, 0x4);
 	printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
-	
+
 	if (!conf->enable_native_ide) {
 		// Use compatability mode - per award bios
 		pci_write_config32(dev, 0x10, 0x0);
 		pci_write_config32(dev, 0x14, 0x0);
 		pci_write_config32(dev, 0x18, 0x0);
 		pci_write_config32(dev, 0x1c, 0x0);
-		
+
 		// Force interrupts to use compat mode - just like Award bios
 		pci_write_config8(dev, 0x3d, 0x0);
 		pci_write_config8(dev, 0x3c, 0xff);
@@ -103,10 +103,10 @@ static struct device_operations ide_ops = {
 	.enable_resources = pci_dev_enable_resources,
 	.init             = ide_init,
 	.enable           = 0,
-	.ops_pci          = 0, 
+	.ops_pci          = 0,
 };
 
-static const struct pci_driver northbridge_driver __pci_driver = { 
+static const struct pci_driver northbridge_driver __pci_driver = {
 	.ops    = &ide_ops,
 	.vendor = PCI_VENDOR_ID_VIA,
 	.device = PCI_DEVICE_ID_VIA_82C586_1,
diff --git a/src/southbridge/via/vt8235/vt8235_lpc.c b/src/southbridge/via/vt8235/vt8235_lpc.c
index 0746bc9a13..e2bfc3681e 100644
--- a/src/southbridge/via/vt8235/vt8235_lpc.c
+++ b/src/southbridge/via/vt8235/vt8235_lpc.c
@@ -88,7 +88,7 @@ static void pci_routing_fixup(struct device *dev)
 	printk(BIOS_INFO, "setting pci slot\n");
 	pci_assign_irqs(0, 0x14, pin_to_irq(slotPins));
 
-	// Cardbus slot 
+	// Cardbus slot
 	printk(BIOS_INFO, "setting cardbus slot\n");
 	pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins));
 
@@ -99,11 +99,11 @@ static void pci_routing_fixup(struct device *dev)
 	printk(BIOS_SPEW, "%s: DONE\n", __func__);
 }
 
-/* 
+/*
  * Set up the power management capabilities directly into ACPI mode.  This
  * avoids having to handle any System Management Interrupts (SMI's) which I
  * can't figure out how to do !!!!
- */ 
+ */
 
 static void setup_pm(device_t dev)
 {
@@ -112,7 +112,7 @@ static void setup_pm(device_t dev)
 
 	// Set ACPI base address to IO 0x4000
 	pci_write_config16(dev, 0x88, 0x0401);
-	
+
 	// set ACPI irq to 5
 	pci_write_config8(dev, 0x82, 0x45);
 
@@ -138,7 +138,7 @@ static void setup_pm(device_t dev)
 	outw(0xffff, 0x420);
 	outw(0xffff, 0x428);
 	outl(0xffffffff, 0x430);
-	
+
 	outw(0x0, 0x424);
 	outw(0x0, 0x42a);
 	outw(0x1, 0x42c);
@@ -152,29 +152,29 @@ static void setup_pm(device_t dev)
 static void vt8235_init(struct device *dev)
 {
 	unsigned char enables;
-	
+
 	printk(BIOS_DEBUG, "vt8235 init\n");
 
 	// enable the internal I/O decode
 	enables = pci_read_config8(dev, 0x6C);
 	enables |= 0x80;
 	pci_write_config8(dev, 0x6C, enables);
-	
+
 	// Map 4MB of FLASH into the address space
 	pci_write_config8(dev, 0x41, 0x7f);
-	
+
 	// Set bit 6 of 0x40, because Award does it (IO recovery time)
-	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI 
+	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
 	// interrupts can be properly marked as level triggered.
 	enables = pci_read_config8(dev, 0x40);
 	enables |= 0x45;
 	pci_write_config8(dev, 0x40, enables);
-	
+
 	// Set 0x42 to 0xf0 to match Award bios
 	enables = pci_read_config8(dev, 0x42);
 	enables |= 0xf0;
 	pci_write_config8(dev, 0x42, enables);
-	
+
 	/* Set 0x58 to 0x03 to match Award */
 	pci_write_config8(dev, 0x58, 0x03);
 
@@ -187,16 +187,16 @@ static void vt8235_init(struct device *dev)
 	enables = pci_read_config8(dev, 0x4a);
 	enables |= 0x08;
 	pci_write_config8(dev, 0x4a, enables);
-	
+
 	// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
 	enables = pci_read_config8(dev, 0x4f);
 	enables |= 0x08;
 	pci_write_config8(dev, 0x4f, enables);
-	
+
 	// Set 0x58 to 0x03 to match Award
 	pci_write_config8(dev, 0x58, 0x03);
-	
-	
+
+
 	/* enable serial irq */
 	pci_write_config8(dev, 0x52, 0x9);
 
@@ -205,10 +205,10 @@ static void vt8235_init(struct device *dev)
 
 	// Power management setup
 	setup_pm(dev);
-	
+
 	/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
 	pci_write_config8(dev, 0x40, 0x54);
-	
+
 	// Start the rtc
 	rtc_init(0);
 }
@@ -248,7 +248,7 @@ static void vt8235_enable_resources(device_t dev)
 	pci_dev_enable_resources(dev);
 	enable_childrens_resources(dev);
 }
-	
+
 static void southbridge_init(struct device *dev)
 {
 	vt8235_init(dev);
diff --git a/src/southbridge/via/vt8235/vt8235_nic.c b/src/southbridge/via/vt8235/vt8235_nic.c
index 86fef895de..71f169c055 100644
--- a/src/southbridge/via/vt8235/vt8235_nic.c
+++ b/src/southbridge/via/vt8235/vt8235_nic.c
@@ -5,7 +5,7 @@
 #include <device/pci_ids.h>
 
 /*
- * Enable the ethernet device and turn off stepping (because it is integrated 
+ * Enable the ethernet device and turn off stepping (because it is integrated
  * inside the southbridge)
  */
 static void nic_init(struct device *dev)