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authorMartin Roth <martin.roth@se-eng.com>2014-12-09 13:49:05 -0700
committerMartin Roth <gaumless@gmail.com>2014-12-17 16:54:21 +0100
commit84422b1a20be7897e3b054ebbfc26f82b0fcdc76 (patch)
tree320d2d8fe7925d0ad01eac93801cc58204a79489 /src/southbridge/via/vt8235
parentb348bb5cfb269ceedfea5dff3dd088cdcf31485a (diff)
downloadcoreboot-84422b1a20be7897e3b054ebbfc26f82b0fcdc76.tar.xz
southbridge/via: Spelling fixes
Change-Id: I7efc441d3da10e48c8c79e4cd51885bb14eebd55 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7730 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge/via/vt8235')
-rw-r--r--src/southbridge/via/vt8235/early_serial.c2
-rw-r--r--src/southbridge/via/vt8235/early_smbus.c2
-rw-r--r--src/southbridge/via/vt8235/ide.c6
-rw-r--r--src/southbridge/via/vt8235/lpc.c8
-rw-r--r--src/southbridge/via/vt8235/vt8235.c2
5 files changed, 10 insertions, 10 deletions
diff --git a/src/southbridge/via/vt8235/early_serial.c b/src/southbridge/via/vt8235/early_serial.c
index 11f98fae39..b9bec5fa08 100644
--- a/src/southbridge/via/vt8235/early_serial.c
+++ b/src/southbridge/via/vt8235/early_serial.c
@@ -1,5 +1,5 @@
/*
- * Enable the serial evices on the VIA
+ * Enable the serial devices on the VIA
*/
diff --git a/src/southbridge/via/vt8235/early_smbus.c b/src/southbridge/via/vt8235/early_smbus.c
index c346b81f6a..c4bca9c210 100644
--- a/src/southbridge/via/vt8235/early_smbus.c
+++ b/src/southbridge/via/vt8235/early_smbus.c
@@ -136,7 +136,7 @@ static void smbus_print_error(unsigned char host_status_register)
print_err_hex8(host_status_register);
print_err("\n");
if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\n");
+ print_err("Interrupt/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
print_err("Bus Error\n");
diff --git a/src/southbridge/via/vt8235/ide.c b/src/southbridge/via/vt8235/ide.c
index 961f860fed..176e70fea7 100644
--- a/src/southbridge/via/vt8235/ide.c
+++ b/src/southbridge/via/vt8235/ide.c
@@ -14,7 +14,7 @@ static void ide_init(struct device *dev)
/*if (!conf->enable_native_ide) { */
/*
- * Run the IDE controller in 'compatiblity mode - i.e. don't
+ * Run the IDE controller in 'compatibility mode - i.e. don't
* use PCI interrupts. Using PCI ints confuses linux for some
* reason.
*/
@@ -22,7 +22,7 @@ static void ide_init(struct device *dev)
__func__);
enables = pci_read_config8(dev, 0x42);
printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables);
- enables &= ~0xc0; // compatability mode
+ enables &= ~0xc0; // compatibility mode
pci_write_config8(dev, 0x42, enables);
enables = pci_read_config8(dev, 0x42);
printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n",
@@ -85,7 +85,7 @@ static void ide_init(struct device *dev)
printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
if (!conf->enable_native_ide) {
- // Use compatability mode - per award bios
+ // Use compatibility mode - per award bios
pci_write_config32(dev, 0x10, 0x0);
pci_write_config32(dev, 0x14, 0x0);
pci_write_config32(dev, 0x18, 0x0);
diff --git a/src/southbridge/via/vt8235/lpc.c b/src/southbridge/via/vt8235/lpc.c
index 2c7848179a..e6aac65375 100644
--- a/src/southbridge/via/vt8235/lpc.c
+++ b/src/southbridge/via/vt8235/lpc.c
@@ -8,7 +8,7 @@
#include <arch/ioapic.h>
#include "chip.h"
-/* The epia-m is really short on interrupts available, so PCI interupts A & D are ganged togther and so are B & C.
+/* The epia-m is really short on interrupts available, so PCI interrupts A & D are ganged together and so are B & C.
This is how the Award bios sets it up too.
epia can be more generous as it does not need to reserve interrupts for cardbus devices, but if changed then
make sure that ACPI dsdt is changed to suit.
@@ -19,7 +19,7 @@
IRQ 3 = COM 2
IRQ 4 = COM 1
IRQ 5 = available for PCI interrupts
- IRQ 6 = floppy or availbale for PCI if floppy controller disabled
+ IRQ 6 = floppy or available for PCI if floppy controller disabled
IRQ 7 = LPT or available if LPT port disabled
IRQ 8 = rtc
IRQ 9 = available for PCI interrupts
@@ -115,7 +115,7 @@ static void setup_pm(device_t dev)
// set ACPI irq to 5
pci_write_config8(dev, 0x82, 0x45);
- // primary interupt channel
+ // primary interrupt channel
pci_write_config16(dev, 0x84, 0x30f2);
// throttle / stop clock control
@@ -212,7 +212,7 @@ static void vt8235_init(struct device *dev)
cmos_init(0);
}
-/* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this
+/* total kludge to get lxb to call our children's set/enable functions - these are not called unless this
device has a resource to set - so set a dummy one */
static void vt8235_read_resources(device_t dev)
{
diff --git a/src/southbridge/via/vt8235/vt8235.c b/src/southbridge/via/vt8235/vt8235.c
index 6bc767ae34..0f37be2aee 100644
--- a/src/southbridge/via/vt8235/vt8235.c
+++ b/src/southbridge/via/vt8235/vt8235.c
@@ -64,7 +64,7 @@ static void vt8235_enable(struct device *dev)
printk(BIOS_DEBUG, "Initialising Devices\n");
- /* make sure interupt controller is configured before keyboard init */
+ /* make sure interrupt controller is configured before keyboard init */
setup_i8259();
/* enable RTC and ethernet */