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authorFlorian Zumbiehl <florz@florz.de>2011-11-01 20:19:35 +0100
committerRudolf Marek <r.marek@assembler.cz>2011-12-02 23:06:20 +0100
commit1b940fd424bbe50fb8792680e2826b7f59a6d1df (patch)
tree453a7e36133984585ca76ec1f5ac2d6cecfdb28b /src/southbridge/via/vt8237r/chip.h
parent28bdd8d9eb7521df60b9cb918320cf2ba9a23e1e (diff)
downloadcoreboot-1b940fd424bbe50fb8792680e2826b7f59a6d1df.tar.xz
implement usb2 termination and dpll delay setting for vt8237r
Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/385 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Diffstat (limited to 'src/southbridge/via/vt8237r/chip.h')
-rw-r--r--src/southbridge/via/vt8237r/chip.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h
index f05d3c0bde..2e24fac4f8 100644
--- a/src/southbridge/via/vt8237r/chip.h
+++ b/src/southbridge/via/vt8237r/chip.h
@@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config {
/* 1 = 80-pin cable, 0 = 40-pin cable */
u8 ide0_80pin_cable;
u8 ide1_80pin_cable;
+
+ u8 usb2_termination_set;
+ u8 usb2_termination_a;
+ u8 usb2_termination_b;
+ u8 usb2_termination_c;
+ u8 usb2_termination_d;
+ u8 usb2_termination_e;
+ u8 usb2_termination_f;
+ u8 usb2_termination_g;
+ u8 usb2_termination_h;
+
+ u8 usb2_dpll_set;
+ u8 usb2_dpll_delay;
};
#endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */