diff options
| author | Jon Harrison <bothlyn@blueyonder.co.uk> | 2009-08-17 17:09:46 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-08-17 17:09:46 +0000 |
| commit | 1825be291f49f892fa8c048974239aa0daa4de56 (patch) | |
| tree | 0451175aed9b7d9f8d5a1cffc0a69ade799c36aa /src/southbridge/via/vt8237r/vt8237r_ide.c | |
| parent | b5f4e77bff5247dc155873f668a0ccf35400cd11 (diff) | |
| download | coreboot-1825be291f49f892fa8c048974239aa0daa4de56.tar.xz | |
Get the Via EPIA-N(L)/CN400 to a reasonable level of maturity::
Tested on Via EPIA-NL8000EG with FILO payload booting FC9 (2.6.25
kernel) from SATA HDD.
ACPI is working for PCI interrupt routing, some memory stuff and
Soft-Off.
USB/SATA Working
VGA Console Working
X Working via Onboard AGP
Removed dsdt.c, fixed some whitespace.
Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via/vt8237r/vt8237r_ide.c')
| -rw-r--r-- | src/southbridge/via/vt8237r/vt8237r_ide.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/src/southbridge/via/vt8237r/vt8237r_ide.c b/src/southbridge/via/vt8237r/vt8237r_ide.c index 9874863c81..acec09ef40 100644 --- a/src/southbridge/via/vt8237r/vt8237r_ide.c +++ b/src/southbridge/via/vt8237r/vt8237r_ide.c @@ -35,8 +35,10 @@ static void ide_init(struct device *dev) struct southbridge_via_vt8237r_config *sb = (struct southbridge_via_vt8237r_config *)dev->chip_info; - u8 enables; + u8 enables, reg8; u32 cablesel; + device_t lpc_dev; + int i, j; printk_info("%s IDE interface %s\n", "Primary", sb->ide0_enable ? "enabled" : "disabled"); @@ -49,6 +51,10 @@ static void ide_init(struct device *dev) printk_debug("Enables in reg 0x40 read back as 0x%x\n", enables); /* Enable only compatibility mode. */ + enables = pci_read_config8(dev, 0x09); + enables &= 0xFA; + pci_write_config8(dev, 0x09, enables); + enables = pci_read_config8(dev, IDE_CONF_II); enables &= ~0xc0; pci_write_config8(dev, IDE_CONF_II, enables); @@ -74,6 +80,7 @@ static void ide_init(struct device *dev) /* Use memory read multiple, Memory-Write-and-Invalidate. */ enables = pci_read_config8(dev, IDE_MISC_II); + enables &= 0xEF; enables |= (1 << 2) | (1 << 3); pci_write_config8(dev, IDE_MISC_II, enables); @@ -89,6 +96,14 @@ static void ide_init(struct device *dev) (sb->ide1_80pin_cable << 12) | (sb->ide1_80pin_cable << 4); pci_write_config32(dev, IDE_UDMA, cablesel); + +#ifdef CONFIG_EPIA_VT8237R_INIT + /* Set PATA Output Drive Strength */ + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (lpc_dev) + pci_write_config8(lpc_dev, 0x7C, 0x20); +#endif } static const struct device_operations ide_ops = { |