diff options
| author | Rudolf Marek <r.marek@assembler.cz> | 2008-12-04 23:37:12 +0000 |
|---|---|---|
| committer | Rudolf Marek <r.marek@assembler.cz> | 2008-12-04 23:37:12 +0000 |
| commit | 31e52e61aa4cbe3065ea86732a689ab4cf58984f (patch) | |
| tree | b7832dc8aa31f7ec64a6742b6be1f2017c9d935f /src/southbridge/via/vt8237r/vt8237r_lpc.c | |
| parent | 1162f25a49e8f39822123d664cda10fef466b351 (diff) | |
| download | coreboot-31e52e61aa4cbe3065ea86732a689ab4cf58984f.tar.xz | |
The patch changes the LDTSTOP length as well mostly default content of 0xec,
0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong.
Furthermore this fix for powernow may not work on CPUs hit by errata #181.
Workaround should be implemented. The powernow may not work on pre-A2 revisions
of VT8237S silicon, revision reg is unknown.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via/vt8237r/vt8237r_lpc.c')
| -rw-r--r-- | src/southbridge/via/vt8237r/vt8237r_lpc.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c index 10d8c35c19..78c973fba0 100644 --- a/src/southbridge/via/vt8237r/vt8237r_lpc.c +++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c @@ -264,14 +264,10 @@ static void vt8237s_init(struct device *dev) pci_write_config32(dev, 0xbc, (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000)); - /* Enable SATA LED, VR timer = 100us, VR timer should be fixed. */ - pci_write_config8(dev, 0xe5, 0x69); - /* * REQ5 as PCI request input - should be together with INTE-INTH. - * Fast VR timer disable - need for LDTSTOP_L signal. */ - pci_write_config8(dev, 0xe4, 0xa5); + pci_write_config8(dev, 0xe4, 0x04); /* Reduce further the STPCLK/LDTSTP signal to 5us. */ pci_write_config8(dev, 0xec, 0x4); |