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authorFlorian Zumbiehl <florz@florz.de>2011-11-21 03:10:47 +0100
committerRudolf Marek <r.marek@assembler.cz>2011-12-02 23:23:24 +0100
commit98236ca7844ec36bf1e43a9d689b55fa409f0a4a (patch)
treeb4970ae761271b446f07a18a6bb53f448bcfbe1b /src/southbridge/via/vt8237r
parent2138556e2aaa70730a58e6a74dd17ed5bc27bcc1 (diff)
downloadcoreboot-98236ca7844ec36bf1e43a9d689b55fa409f0a4a.tar.xz
make INT[EFGH]# of vt8237 configurable as gpio via devicetree
Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/386 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Diffstat (limited to 'src/southbridge/via/vt8237r')
-rw-r--r--src/southbridge/via/vt8237r/chip.h2
-rw-r--r--src/southbridge/via/vt8237r/lpc.c9
2 files changed, 10 insertions, 1 deletions
diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h
index 2e24fac4f8..bbba5e4d85 100644
--- a/src/southbridge/via/vt8237r/chip.h
+++ b/src/southbridge/via/vt8237r/chip.h
@@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config {
u8 usb2_dpll_set;
u8 usb2_dpll_delay;
+
+ u8 int_efgh_as_gpio;
};
#endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 207dfdb335..43a9394bfa 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -421,10 +421,13 @@ static void vt8237s_init(struct device *dev)
static void vt8237_common_init(struct device *dev)
{
u8 enables, byte;
+ struct southbridge_via_vt8237r_config *cfg;
#if !CONFIG_EPIA_VT8237R_INIT
unsigned char pwr_on;
#endif
+ cfg = dev->chip_info;
+
/* Enable addr/data stepping. */
byte = pci_read_config8(dev, PCI_COMMAND);
byte |= PCI_COMMAND_WAIT;
@@ -509,7 +512,11 @@ static void vt8237_common_init(struct device *dev)
* | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
* 0 | Dynamic Clock Gating Main Switch (1=Enable)
*/
- pci_write_config8(dev, 0x5b, 0xb);
+ if (cfg && cfg->int_efgh_as_gpio) {
+ pci_write_config8(dev, 0x5b, 0x9);
+ } else {
+ pci_write_config8(dev, 0x5b, 0xb);
+ }
/* configure power state of the board after loss of power */
if (get_option(&pwr_on, "power_on_after_fail") < 0)