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| author | Marc Jones <marcj303@gmail.com> | 2011-06-03 19:59:52 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-06-03 19:59:52 +0000 |
| commit | 471f103e530b97c1125acdab259043dd7f252fe9 (patch) | |
| tree | f398b52a2d3ae8f9569a851151bfeb02bf4026a9 /src/southbridge/via/vt8237r | |
| parent | 23d3dfaa96649c71295de205885e97c6b45f9183 (diff) | |
| download | coreboot-471f103e530b97c1125acdab259043dd7f252fe9.tar.xz | |
This patch sets max freq defaults for ddr2 and ddr3for fam10.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via/vt8237r')
0 files changed, 0 insertions, 0 deletions