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| author | Rudolf Marek <r.marek@assembler.cz> | 2009-04-13 18:00:09 +0000 |
|---|---|---|
| committer | Rudolf Marek <r.marek@assembler.cz> | 2009-04-13 18:00:09 +0000 |
| commit | 497c8effceb9510ca89561a8fcc87cbc0acb8b08 (patch) | |
| tree | aaaeaeda460a8f7c351488a424678bcefc211d9f /src/southbridge/via/vt8237r | |
| parent | a572f83e7198eff99728335e697e9a0ef1e53a0c (diff) | |
| download | coreboot-497c8effceb9510ca89561a8fcc87cbc0acb8b08.tar.xz | |
Following patch adds support for resume on VT8237 based motherboards. The NB
part of this patch adds support for resume well NVRAM. In which DQS values are
stored.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via/vt8237r')
| -rw-r--r-- | src/southbridge/via/vt8237r/vt8237r_early_smbus.c | 31 | ||||
| -rw-r--r-- | src/southbridge/via/vt8237r/vt8237r_lpc.c | 23 |
2 files changed, 50 insertions, 4 deletions
diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c index 49f3d90020..17b32d529f 100644 --- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c +++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c @@ -294,6 +294,37 @@ void enable_rom_decode(void) pci_write_config8(dev, 0x41, 0x7f); } +#define ACPI_IS_WAKEUP_EARLY 1 + +int acpi_is_wakeup_early(void) { + device_t dev; + u16 tmp; + + print_debug("IN TEST WAKEUP\n"); + + /* Power management controller */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + if (dev == PCI_DEV_INVALID) { + /* Power management controller */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); + if (dev == PCI_DEV_INVALID) + die("Power management controller not found\r\n"); + } + + /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ + pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); + + /* Enable ACPI accessm RTC signal gated with PSON. */ + pci_write_config8(dev, 0x81, 0x84); + + tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); + + print_debug_hex8(tmp); + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; +} + #if defined(__GNUC__) void vt8237_early_spi_init(void) { diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c index 4fbc29575a..d33dc48231 100644 --- a/src/southbridge/via/vt8237r/vt8237r_lpc.c +++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c @@ -149,8 +149,13 @@ static void pci_routing_fixup(struct device *dev) * Set up the power management capabilities directly into ACPI mode. * This avoids having to handle any System Management Interrupts (SMIs). */ + +extern u8 acpi_slp_type; + + static void setup_pm(device_t dev) { + u16 tmp; /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -171,10 +176,10 @@ static void setup_pm(device_t dev) /* * 7 = SMBus clock from RTC 32.768KHz - * 5 = Internal PLL reset from susp - * 2 = GPO2 is GPIO + * 5 = Internal PLL reset from susp disabled + * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa4); + pci_write_config8(dev, 0x94, 0xa0); /* * 7 = stp to sust delay 1msec @@ -219,7 +224,17 @@ static void setup_pm(device_t dev) outb(0x0, VT8237R_ACPI_IO_BASE + 0x42); /* SCI is generated for RTC/pwrBtn/slpBtn. */ - outw(0x001, VT8237R_ACPI_IO_BASE + 0x04); + tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); + acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; + printk_debug("SLP_TYP type was %x %x\n", tmp, acpi_slp_type); + /* clear sleep */ + tmp &= ~(7 << 10); + tmp |= 1; + outw(tmp, VT8237R_ACPI_IO_BASE + 0x04); + + + + } static void vt8237r_init(struct device *dev) |