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authorStefan Reinauer <reinauer@chromium.org>2014-12-19 13:45:24 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-01-06 18:20:32 +0100
commit8de452da2e3219eebd337927c62ddda50ca38323 (patch)
tree14b7ef14804900e8924cfa6989f1e7c155b95bd6 /src/southbridge/via/vt8237r
parent897123ab2f3bcde00848ae622faeb2ca1e7004f0 (diff)
downloadcoreboot-8de452da2e3219eebd337927c62ddda50ca38323.tar.xz
Drop VIA VT8235 southbridge
It's unused. Change-Id: Iad3e7aa0f777392c9d65b9fcdd3c1666af31723a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7883 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge/via/vt8237r')
-rw-r--r--src/southbridge/via/vt8237r/early_serial.c77
1 files changed, 77 insertions, 0 deletions
diff --git a/src/southbridge/via/vt8237r/early_serial.c b/src/southbridge/via/vt8237r/early_serial.c
new file mode 100644
index 0000000000..9143f4690a
--- /dev/null
+++ b/src/southbridge/via/vt8237r/early_serial.c
@@ -0,0 +1,77 @@
+/*
+ * Enable the serial devices on the VIA
+ */
+
+
+/* The base address is 0x15c, 0x2e, depending on config bytes */
+
+#define SIO_BASE 0x3f0
+#define SIO_DATA SIO_BASE+1
+
+static void vt8237r_writepnpaddr(uint8_t val)
+{
+ outb(val, 0x2e);
+ outb(val, 0xeb);
+}
+
+static void vt8237r_writepnpdata(uint8_t val)
+{
+ outb(val, 0x2f);
+ outb(val, 0xeb);
+}
+
+
+static void vt8237r_writesiobyte(uint16_t reg, uint8_t val)
+{
+ outb(val, reg);
+}
+
+static void vt8237r_writesioword(uint16_t reg, uint16_t val)
+{
+ outw(val, reg);
+}
+
+
+/* regs we use: 85, and the southbridge devfn is defined by the
+ mainboard
+ */
+
+static void enable_vt8237r_serial(void)
+{
+ // turn on pnp
+ vt8237r_writepnpaddr(0x87);
+ vt8237r_writepnpaddr(0x87);
+ // now go ahead and set up com1.
+ // set address
+ vt8237r_writepnpaddr(0x7);
+ vt8237r_writepnpdata(0x2);
+ // enable serial out
+ vt8237r_writepnpaddr(0x30);
+ vt8237r_writepnpdata(0x1);
+ // serial port 1 base address (FEh)
+ vt8237r_writepnpaddr(0x60);
+ vt8237r_writepnpdata(0xfe);
+ // serial port 1 IRQ (04h)
+ vt8237r_writepnpaddr(0x70);
+ vt8237r_writepnpdata(0x4);
+ // serial port 1 control
+ vt8237r_writepnpaddr(0xf0);
+ vt8237r_writepnpdata(0x2);
+ // turn of pnp
+ vt8237r_writepnpaddr(0xaa);
+
+ // set up reg to set baud rate.
+ vt8237r_writesiobyte(0x3fb, 0x80);
+ // Set 115 kb
+ vt8237r_writesioword(0x3f8, 1);
+ // Set 9.6 kb
+ // WRITESIOWORD(0x3f8, 12)
+ // now set no parity, one stop, 8 bits
+ vt8237r_writesiobyte(0x3fb, 3);
+ // now turn on RTS, DRT
+ vt8237r_writesiobyte(0x3fc, 3);
+ // Enable interrupts
+ vt8237r_writesiobyte(0x3f9, 0xf);
+ // should be done. Dump a char for fun.
+ vt8237r_writesiobyte(0x3f8, 48);
+}