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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-24 00:26:26 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-31 03:41:41 +0000 |
| commit | 4979ffc5cb267c7b0a5ad84c8bb9729e6b5613b1 (patch) | |
| tree | c675c0b95a558ece1233c19d69d40f7441cfa500 /src/southbridge/via/vt8237r | |
| parent | 1740230ace3aeede3a7ee5cadd1e17744cda07b3 (diff) | |
| download | coreboot-4979ffc5cb267c7b0a5ad84c8bb9729e6b5613b1.tar.xz | |
Remove southbridges after K8 board removals
Change-Id: Ib6935c026e2302b037fc82be64163f10bf775751
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/via/vt8237r')
| -rw-r--r-- | src/southbridge/via/vt8237r/lpc.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 46b1e237fd..998340f419 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -319,21 +319,11 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0x48, 0x0c); #else - - #if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD) - /* It seems that when we pair with the K8T800, we need to disable - * the A2 mask - */ - pci_write_config8(dev, 0x48, 0x0c); - #else /* * Set Read Pass Write Control Enable * (force A2 from APIC FSB to low). */ pci_write_config8(dev, 0x48, 0x8c); - #endif - #endif southbridge_init_common(dev); |