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authorStefan Reinauer <stepan@coresystems.de>2010-04-14 18:59:42 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-14 18:59:42 +0000
commit523ebd927d80807fa8a8c30cddfe0f549b7f62d8 (patch)
treed26cc7520f89d16260fa1cd989512834bb7dc962 /src/southbridge/via/vt8237r
parent97b21be8c74a2e9da5a7c01944a727e0bab05170 (diff)
downloadcoreboot-523ebd927d80807fa8a8c30cddfe0f549b7f62d8.tar.xz
zero warning days. Move RAMTOP and RAMBASE together.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via/vt8237r')
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_usb.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/southbridge/via/vt8237r/vt8237r_usb.c b/src/southbridge/via/vt8237r/vt8237r_usb.c
index 4bd33d6346..6e8d9e5dd0 100644
--- a/src/southbridge/via/vt8237r/vt8237r_usb.c
+++ b/src/southbridge/via/vt8237r/vt8237r_usb.c
@@ -30,16 +30,15 @@ u32 usb_io_addr[4] = {0xcc00, 0xd000, 0xd400, 0xd800};
static void usb_i_init(struct device *dev)
{
-
#if CONFIG_EPIA_VT8237R_INIT
u8 reg8;
printk(BIOS_DEBUG, "Entering %s\n", __func__);
- printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8);
-
reg8 = pci_read_config8(dev, 0x04);
+ printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8);
+
reg8 = reg8 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config8(dev, 0x04, reg8);