src/southbridge: add IS_ENABLED() around Kconfig symbol references

Change-Id: Ie965cbcf7f7b6f6c9e9a69e2a1ff0ba491246cbe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

6 files changed, 23 insertions, 22 deletions

diff --git a/src/southbridge/via/vt8237r/ide.c b/src/southbridge/via/vt8237r/ide.c
index 8550d46a09..457917174d 100644
--- a/src/southbridge/via/vt8237r/ide.c
+++ b/src/southbridge/via/vt8237r/ide.c
@@ -101,7 +101,7 @@ static void ide_init(struct device *dev)
 	cablesel |= vt8237_ide_80pin_detect(dev);
 	pci_write_config32(dev, IDE_UDMA, cablesel);
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	device_t lpc_dev;
 
 	/* Set PATA Output Drive Strength */
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 9d91749379..70ac5d9cc6 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -34,7 +34,7 @@
 
 static void southbridge_init_common(struct device *dev);
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
                    /* Interrupts for  INT# A   B   C   D */
 static const unsigned char pciIrqs[4]  = { 10, 11, 12, 0};
 
@@ -61,7 +61,7 @@ static unsigned char *pin_to_irq(const unsigned char *pin)
 /** Set up PCI IRQ routing, route everything through APIC. */
 static void pci_routing_fixup(struct device *dev)
 {
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	device_t pdev;
 #endif
 
@@ -74,7 +74,7 @@ static void pci_routing_fixup(struct device *dev)
 	/* Gate Interrupts until RAM Writes are flushed */
 	pci_write_config8(dev, 0x49, 0x20);
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 
 	/* Share INTE-INTH with INTA-INTD as per stock BIOS. */
 	pci_write_config8(dev, 0x46, 0x00);
@@ -160,7 +160,7 @@ static void setup_pm(device_t dev)
 	/* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */
 	pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ);
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	/* Primary interrupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
 	pci_write_config16(dev, 0x84, 0x3052);
 #else
@@ -195,7 +195,7 @@ static void setup_pm(device_t dev)
 	 * 0 = USB Wakeup
 	 */
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	pci_write_config8(dev, 0x95, 0xc2);
 #else
 	tmp = 0xcc;
@@ -263,7 +263,7 @@ static void vt8237r_init(struct device *dev)
 
 	cfg = dev->chip_info;
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n");
 	/*
 	 * TODO: Looks like stock BIOS can do this but causes a hang
@@ -313,14 +313,15 @@ static void vt8237r_init(struct device *dev)
 	enables |= 0x08;
 	pci_write_config8(dev, 0x4f, enables);
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	/*
 	 * Set Read Pass Write Control Enable
 	 */
 	pci_write_config8(dev, 0x48, 0x0c);
 #else
 
-  #if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
+  #if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800) || \
+	IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
 	/* It seems that when we pair with the K8T800, we need to disable
 	 * the A2 mask
 	 */
@@ -337,7 +338,7 @@ static void vt8237r_init(struct device *dev)
 
 	southbridge_init_common(dev);
 
-#if !CONFIG_EPIA_VT8237R_INIT
+#if !IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	/* FIXME: Intel needs more bit set for C2/C3. */
 
 	/*
@@ -444,7 +445,7 @@ static void vt8237_common_init(struct device *dev)
 {
 	u8 enables, byte;
 	struct southbridge_via_vt8237r_config *cfg;
-#if !CONFIG_EPIA_VT8237R_INIT
+#if !IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	unsigned char pwr_on;
 #endif
 
@@ -456,7 +457,7 @@ static void vt8237_common_init(struct device *dev)
 	pci_write_config8(dev, PCI_COMMAND, byte);
 
 /* EPIA-N(L) Uses CN400 for BIOS Access */
-#if !CONFIG_EPIA_VT8237R_INIT
+#if !IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	/* Enable the internal I/O decode. */
 	enables = pci_read_config8(dev, 0x6C);
 	enables |= 0x80;
@@ -495,7 +496,7 @@ static void vt8237_common_init(struct device *dev)
 	/* Delay transaction control */
 	pci_write_config8(dev, 0x43, 0xb);
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	/* I/O recovery time, default IDE routing */
 	pci_write_config8(dev, 0x4c, 0x04);
 
@@ -555,7 +556,7 @@ static void vt8237_common_init(struct device *dev)
 	/* Enable serial IRQ, 6PCI clocks. */
 	pci_write_config8(dev, 0x52, 0x9);
 #endif
-#if CONFIG_HAVE_SMI_HANDLER
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
 	smm_lock();
 #endif
 
diff --git a/src/southbridge/via/vt8237r/nic.c b/src/southbridge/via/vt8237r/nic.c
index ebebd37a79..aa6048916a 100644
--- a/src/southbridge/via/vt8237r/nic.c
+++ b/src/southbridge/via/vt8237r/nic.c
@@ -23,7 +23,7 @@
 
 static void vt8237_eth_read_resources(struct device *dev)
 {
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	struct resource *res;
 
 	/* Fix the I/O Resources of the USB2.0 Interface */
diff --git a/src/southbridge/via/vt8237r/pirq.c b/src/southbridge/via/vt8237r/pirq.c
index ec393b49f0..fd55b1fc9d 100644
--- a/src/southbridge/via/vt8237r/pirq.c
+++ b/src/southbridge/via/vt8237r/pirq.c
@@ -21,7 +21,7 @@
 #include <device/pci_ids.h>
 #include <pc80/i8259.h>
 
-#if (CONFIG_PIRQ_ROUTE == 1 && CONFIG_GENERATE_PIRQ_TABLE == 1)
+#if IS_ENABLED(CONFIG_PIRQ_ROUTE) && IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE)
 void pirq_assign_irqs(const unsigned char route[4])
 {
 	device_t pdev;
diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c
index 42da53a8f2..057a07ddae 100644
--- a/src/southbridge/via/vt8237r/usb.c
+++ b/src/southbridge/via/vt8237r/usb.c
@@ -21,13 +21,13 @@
 #include "chip.h"
 #include "vt8237r.h"
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 u32 usb_io_addr[4] = {0xcc00, 0xd000, 0xd400, 0xd800};
 #endif
 
 static void usb_i_init(struct device *dev)
 {
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	u8 reg8;
 
 	printk(BIOS_DEBUG, "Entering %s\n", __func__);
@@ -66,7 +66,7 @@ static void usb_i_init(struct device *dev)
 
 static void vt8237_usb_i_read_resources(struct device *dev)
 {
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	struct resource *res;
 	u8 function = (u8) dev->path.pci.devfn & 0x7;
 
@@ -92,7 +92,7 @@ static void vt8237_usb_i_read_resources(struct device *dev)
 static void usb_ii_init(struct device *dev)
 {
 	struct southbridge_via_vt8237r_config *cfg;
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	u8 reg8;
 
 	printk(BIOS_DEBUG, "Entering %s\n", __func__);
@@ -136,7 +136,7 @@ static void usb_ii_init(struct device *dev)
 
 static void vt8237_usb_ii_read_resources(struct device *dev)
 {
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	struct resource *res;
 
 	/* Fix the I/O Resources of the USB2.0 Interface */
diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h
index e195a299d9..d4cc771536 100644
--- a/src/southbridge/via/vt8237r/vt8237r.h
+++ b/src/southbridge/via/vt8237r/vt8237r.h
@@ -91,7 +91,7 @@
 #define I2C_TRANS_CMD			0x40
 #define CLOCK_SLAVE_ADDRESS		0x69
 
-#if CONFIG_DEBUG_SMBUS
+#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
 #define PRINT_DEBUG(x)		printk(BIOS_DEBUG, x)
 #define PRINT_DEBUG_HEX16(x)	printk(BIOS_DEBUG, "%04x", x)
 #else