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authorFlorian Zumbiehl <florz@florz.de>2011-11-01 20:19:35 +0100
committerRudolf Marek <r.marek@assembler.cz>2011-12-02 23:06:20 +0100
commit1b940fd424bbe50fb8792680e2826b7f59a6d1df (patch)
tree453a7e36133984585ca76ec1f5ac2d6cecfdb28b /src/southbridge/via
parent28bdd8d9eb7521df60b9cb918320cf2ba9a23e1e (diff)
downloadcoreboot-1b940fd424bbe50fb8792680e2826b7f59a6d1df.tar.xz
implement usb2 termination and dpll delay setting for vt8237r
Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/385 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Diffstat (limited to 'src/southbridge/via')
-rw-r--r--src/southbridge/via/vt8237r/chip.h13
-rw-r--r--src/southbridge/via/vt8237r/usb.c24
2 files changed, 37 insertions, 0 deletions
diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h
index f05d3c0bde..2e24fac4f8 100644
--- a/src/southbridge/via/vt8237r/chip.h
+++ b/src/southbridge/via/vt8237r/chip.h
@@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config {
/* 1 = 80-pin cable, 0 = 40-pin cable */
u8 ide0_80pin_cable;
u8 ide1_80pin_cable;
+
+ u8 usb2_termination_set;
+ u8 usb2_termination_a;
+ u8 usb2_termination_b;
+ u8 usb2_termination_c;
+ u8 usb2_termination_d;
+ u8 usb2_termination_e;
+ u8 usb2_termination_f;
+ u8 usb2_termination_g;
+ u8 usb2_termination_h;
+
+ u8 usb2_dpll_set;
+ u8 usb2_dpll_delay;
};
#endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */
diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c
index 6e8d9e5dd0..2bdcf9d4ba 100644
--- a/src/southbridge/via/vt8237r/usb.c
+++ b/src/southbridge/via/vt8237r/usb.c
@@ -22,6 +22,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include "chip.h"
#include "vt8237r.h"
#if CONFIG_EPIA_VT8237R_INIT
@@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev)
static void usb_ii_init(struct device *dev)
{
+ struct southbridge_via_vt8237r_config *cfg;
#if CONFIG_EPIA_VT8237R_INIT
u8 reg8;
@@ -112,6 +114,28 @@ static void usb_ii_init(struct device *dev)
pci_write_config16(dev, 0x06, 0x7A10);
#endif
+ cfg = dev->chip_info;
+
+ if (cfg) {
+ if (cfg->usb2_termination_set) {
+ /* High Speed Port Pad Termination Resistor Fine Tune */
+ pci_write_config8(dev, 0x5a, cfg->usb2_termination_c |
+ (cfg->usb2_termination_d << 4));
+ pci_write_config8(dev, 0x5b, cfg->usb2_termination_a |
+ (cfg->usb2_termination_b << 4));
+ pci_write_config8(dev, 0x5d, cfg->usb2_termination_e |
+ (cfg->usb2_termination_f << 4));
+ pci_write_config8(dev, 0x5e, cfg->usb2_termination_g |
+ (cfg->usb2_termination_h << 4));
+ }
+
+ if (cfg->usb2_dpll_set) {
+ /* Delay DPLL Input Data Control */
+ pci_write_config8(dev, 0x5c,
+ (pci_read_config8(dev, 0x5c) & ~0x70) |
+ (cfg->usb2_dpll_delay << 4));
+ }
+ }
}
static void vt8237_usb_ii_read_resources(struct device *dev)