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authorFlorian Zumbiehl <florz@florz.de>2011-11-01 20:19:38 +0100
committerRudolf Marek <r.marek@assembler.cz>2011-12-02 23:11:56 +0100
commit6a3e8d62f852f2abd377d827c0909aa71c44ca39 (patch)
tree59b71929ec1b1c5838746c3585797ce05c7f96c4 /src/southbridge/via
parent1b940fd424bbe50fb8792680e2826b7f59a6d1df (diff)
downloadcoreboot-6a3e8d62f852f2abd377d827c0909aa71c44ca39.tar.xz
some black magic for initializing the old version of the k8t800
Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/388 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Diffstat (limited to 'src/southbridge/via')
-rw-r--r--src/southbridge/via/k8t890/bridge.c9
-rw-r--r--src/southbridge/via/k8t890/ctrl.c11
2 files changed, 20 insertions, 0 deletions
diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c
index 1b21b32166..ecfdc3567a 100644
--- a/src/southbridge/via/k8t890/bridge.c
+++ b/src/southbridge/via/k8t890/bridge.c
@@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev)
writeback(dev, 0x40, 0x91);
writeback(dev, 0x41, 0x40);
writeback(dev, 0x43, 0x44);
+#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
+ writeback(dev, 0x42, 0x80);
+ writeback(dev, 0x44, 0x35);
+#else
writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet
* says it is reserved
*/
+#endif
writeback(dev, 0x45, 0x3a);
writeback(dev, 0x46, 0x88); /* PCI ID lo */
writeback(dev, 0x47, 0xb1); /* PCI ID hi */
@@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev)
* (Forward VGA compatible memory and I/O cycles )
*/
+#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
+ writeback(dev, 0x3e, 0x0a);
+#else
writeback(dev, 0x3e, 0x16);
+#endif
dump_south(dev);
/* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */
diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c
index 3180412b90..6e5dbf787c 100644
--- a/src/southbridge/via/k8t890/ctrl.c
+++ b/src/southbridge/via/k8t890/ctrl.c
@@ -51,12 +51,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb)
pci_write_config8(dev, 0x70, 0xc2);
/* PCI Control */
+#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
pci_write_config8(dev, 0x72, 0xee);
+#endif
pci_write_config8(dev, 0x73, 0x01);
+#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
+ pci_write_config8(dev, 0x74, 0x64);
+ pci_write_config8(dev, 0x75, 0x3f);
+#else
pci_write_config8(dev, 0x74, 0x24);
pci_write_config8(dev, 0x75, 0x0f);
+#endif
pci_write_config8(dev, 0x76, 0x50);
+#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
pci_write_config8(dev, 0x77, 0x08);
+#endif
pci_write_config8(dev, 0x78, 0x01);
/* APIC on HT */
pci_write_config8(dev, 0x7c, 0x7f);
@@ -151,7 +160,9 @@ static void ctrl_init(struct device *dev)
/* PCI CFG Address bits[27:24] are used as extended register address
bit[11:8] */
+#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
pci_write_config8(dev, 0x47, 0x30);
+#endif
/* VT8237R specific configuration other SB are done in their own directories */