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authorUwe Hermann <uwe@hermann-uwe.de>2010-10-12 17:34:08 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-10-12 17:34:08 +0000
commit74d1a6e8a166cd477f667a6fcb1e96b8a0cbdac1 (patch)
tree9cbdbe86bd282da60bfcbef7108ca6790bcde94e /src/southbridge/via
parent4ffde94c4ec51cdb24103ec13653e6f40513e1bb (diff)
downloadcoreboot-74d1a6e8a166cd477f667a6fcb1e96b8a0cbdac1.tar.xz
We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.
As both ioapic.h and acpi.h define a macro named "NMI", rename one of them (NMI -> NMIType in acpi.h). Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via')
-rw-r--r--src/southbridge/via/vt8231/vt8231_lpc.c5
-rw-r--r--src/southbridge/via/vt8235/vt8235_lpc.c5
-rw-r--r--src/southbridge/via/vt8237r/vt8237r.h1
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_lpc.c4
4 files changed, 6 insertions, 9 deletions
diff --git a/src/southbridge/via/vt8231/vt8231_lpc.c b/src/southbridge/via/vt8231/vt8231_lpc.c
index fadbcf2fb7..a063adf710 100644
--- a/src/southbridge/via/vt8231/vt8231_lpc.c
+++ b/src/southbridge/via/vt8231/vt8231_lpc.c
@@ -3,9 +3,8 @@
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
-
#include <pc80/mc146818rtc.h>
-
+#include <arch/ioapic.h>
#include "chip.h"
/* PIRQ init
@@ -141,7 +140,7 @@ static void vt8231_read_resources(device_t dev)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
diff --git a/src/southbridge/via/vt8235/vt8235_lpc.c b/src/southbridge/via/vt8235/vt8235_lpc.c
index 15ff5392b2..b355ad0d88 100644
--- a/src/southbridge/via/vt8235/vt8235_lpc.c
+++ b/src/southbridge/via/vt8235/vt8235_lpc.c
@@ -4,9 +4,8 @@
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
-
#include <pc80/mc146818rtc.h>
-
+#include <arch/ioapic.h>
#include "chip.h"
/* The epia-m is really short on interrupts available, so PCI interupts A & D are ganged togther and so are B & C.
@@ -228,7 +227,7 @@ static void vt8235_read_resources(device_t dev)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h
index d54c533aee..ba7089b414 100644
--- a/src/southbridge/via/vt8237r/vt8237r.h
+++ b/src/southbridge/via/vt8237r/vt8237r.h
@@ -35,7 +35,6 @@
#define VT8237S_SPI_MEM_BASE 0xfed02000UL
#endif
#define VT8237R_HPET_ADDR 0xfed00000ULL
-#define VT8237R_APIC_BASE 0xfec00000ULL
/* IDE */
#define IDE_CS 0x40
diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c
index 3074bc8c3c..2de64f03ce 100644
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c
@@ -490,7 +490,7 @@ static void vt8237r_read_resources(device_t dev)
/* Fixed APIC resource */
res = new_resource(dev, 0x44);
- res->base = VT8237R_APIC_BASE;
+ res->base = IO_APIC_ADDR;
res->size = 256;
res->limit = 0xffffffffUL;
res->align = 8;
@@ -516,7 +516,7 @@ static void southbridge_init_common(struct device *dev)
{
vt8237_common_init(dev);
pci_routing_fixup(dev);
- setup_ioapic(VT8237R_APIC_BASE, VT8237R_APIC_ID);
+ setup_ioapic(IO_APIC_ADDR, VT8237R_APIC_ID);
setup_i8259();
init_keyboard(dev);
}