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authorPatrick Georgi <patrick@georgi-clan.de>2012-10-05 21:54:38 +0200
committerPatrick Georgi <patrick@georgi-clan.de>2012-10-08 21:23:08 +0200
commit9aeb69447d3839675b2cac51c3e95a4724fd9b0d (patch)
treed9b1cc7483a51ab340d6d9fae78a30e562f99767 /src/southbridge/via
parentec2c18ee6068ef6adf6f5be437d7047c91773654 (diff)
downloadcoreboot-9aeb69447d3839675b2cac51c3e95a4724fd9b0d.tar.xz
hpet: common ACPI generation
HPET's min ticks (minimum time between events to avoid losing interrupts) is chipset specific, so move it to Kconfig. Via also has a special base address, so move it as well. Apart from these (and the base address was already #defined), the table is very uniform. Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1562 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Diffstat (limited to 'src/southbridge/via')
-rw-r--r--src/southbridge/via/vt8237r/lpc.c8
-rw-r--r--src/southbridge/via/vt8237r/vt8237r.h1
2 files changed, 4 insertions, 5 deletions
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index a47ab38a56..1d96560d03 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -387,8 +387,8 @@ static void vt8237a_init(struct device *dev)
/* Host Bus Power Management Control, maybe not needed */
pci_write_config8(dev, 0x8c, 0x5);
- /* Enable HPET at VT8237R_HPET_ADDR. */
- pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
+ /* Enable HPET */
+ pci_write_config32(dev, 0x68, (CONFIG_HPET_ADDRESS | 0x80));
southbridge_init_common(dev);
@@ -426,8 +426,8 @@ static void vt8237s_init(struct device *dev)
/* Host Bus Power Management Control, maybe not needed */
pci_write_config8(dev, 0x8c, 0x5);
- /* Enable HPET at VT8237R_HPET_ADDR., does not work correctly on R. */
- pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
+ /* Enable HPET, does not work correctly on R. */
+ pci_write_config32(dev, 0x68, (CONFIG_HPET_ADDRESS | 0x80));
southbridge_init_common(dev);
diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h
index 9d5a1fc608..58cb85735a 100644
--- a/src/southbridge/via/vt8237r/vt8237r.h
+++ b/src/southbridge/via/vt8237r/vt8237r.h
@@ -33,7 +33,6 @@
#else
#define VT8237S_SPI_MEM_BASE 0xfed02000UL
#endif
-#define VT8237R_HPET_ADDR 0xfed00000ULL
/* PMBASE FIXME mostly taken from ich7 */
#define PM1_STS 0x00