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| author | Matt DeVillier <matt.devillier@gmail.com> | 2017-11-01 00:29:34 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-03 21:57:52 +0000 |
| commit | e3d8471a7817250ee3f9e68d5612fa26d380825b (patch) | |
| tree | 052175352a9c24bccbdc3cff4a74fec1d18b9407 /src/southbridge/via | |
| parent | 158170b0a8128780df7dded2e24be067133c8a7d (diff) | |
| download | coreboot-e3d8471a7817250ee3f9e68d5612fa26d380825b.tar.xz | |
google/reks: override USB2 Phy settings on BSW D-Stepping SOC
Adapted from Chromium commit 12ad5b5: Reks : override USB2 Phy settings...
Base on Intel recommendation, override following
settings for USB2 port 1/2/3 on BSW D-stepping SOC.
1. Set USB[1] register for right side to 7321
2. Set USB[2] register for left side to 7021
3. Set USB[3] register for CCD to 7021
Original-Change-Id: I04240a010e875f29c47f4fea83ff918f180b0273
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Change-Id: Iabd6312576e9897315c4e4dbf19341380d9d1414
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/via')
0 files changed, 0 insertions, 0 deletions