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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-24 00:26:26 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-31 03:41:41 +0000
commit4979ffc5cb267c7b0a5ad84c8bb9729e6b5613b1 (patch)
treec675c0b95a558ece1233c19d69d40f7441cfa500 /src/southbridge/via
parent1740230ace3aeede3a7ee5cadd1e17744cda07b3 (diff)
downloadcoreboot-4979ffc5cb267c7b0a5ad84c8bb9729e6b5613b1.tar.xz
Remove southbridges after K8 board removals
Change-Id: Ib6935c026e2302b037fc82be64163f10bf775751 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/via')
-rw-r--r--src/southbridge/via/k8t890/Kconfig54
-rw-r--r--src/southbridge/via/k8t890/Makefile.inc16
-rw-r--r--src/southbridge/via/k8t890/acpi/sleepstates.asl31
-rw-r--r--src/southbridge/via/k8t890/bridge.c80
-rw-r--r--src/southbridge/via/k8t890/chrome.c173
-rw-r--r--src/southbridge/via/k8t890/ctrl.c206
-rw-r--r--src/southbridge/via/k8t890/dram.c197
-rw-r--r--src/southbridge/via/k8t890/early_car.c185
-rw-r--r--src/southbridge/via/k8t890/error.c65
-rw-r--r--src/southbridge/via/k8t890/host.c149
-rw-r--r--src/southbridge/via/k8t890/host_ctrl.c160
-rw-r--r--src/southbridge/via/k8t890/k8t890.h56
-rw-r--r--src/southbridge/via/k8t890/k8x8xx.h42
-rw-r--r--src/southbridge/via/k8t890/pcie.c162
-rw-r--r--src/southbridge/via/k8t890/romstrap.S101
-rw-r--r--src/southbridge/via/k8t890/romstrap.ld25
-rw-r--r--src/southbridge/via/k8t890/traf_ctrl.c195
-rw-r--r--src/southbridge/via/vt8237r/lpc.c10
18 files changed, 0 insertions, 1907 deletions
diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig
deleted file mode 100644
index f6e51dccd1..0000000000
--- a/src/southbridge/via/k8t890/Kconfig
+++ /dev/null
@@ -1,54 +0,0 @@
-
-config SOUTHBRIDGE_VIA_K8T890
- bool
-
-if SOUTHBRIDGE_VIA_K8T890
-
-config SOUTHBRIDGE_VIA_SUBTYPE_K8M800 # not tested
- def_bool n
-config SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD # not tested, lspci lists B188 and 3188
- def_bool n
-config SOUTHBRIDGE_VIA_SUBTYPE_K8T800 # lspci lists 0282, 1282, 2282, 3282, and 7282
- def_bool n
-config SOUTHBRIDGE_VIA_SUBTYPE_K8T800PRO # lspci lists 0282, 1282, 2282, 3282, and 7282
- def_bool n
-config SOUTHBRIDGE_VIA_SUBTYPE_K8M890
- def_bool n
-config SOUTHBRIDGE_VIA_SUBTYPE_K8T890
- def_bool n
-
-config SOUTHBRIDGE_VIA_K8M890_VGA_EN
- bool "Enable onboard K8M890 graphics"
- default y
- depends on SOUTHBRIDGE_VIA_SUBTYPE_K8M890
- select VGA
- select GFXUMA
-
-choice
- prompt "Framebuffer size"
- default K8M890_VIDEO_MB_32MB
- depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
-
-config K8M890_VIDEO_MB_32MB
- bool "32MB"
-config K8M890_VIDEO_MB_64MB
- bool "64MB"
-config K8M890_VIDEO_MB_128MB
- bool "128MB"
-config K8M890_VIDEO_MB_256MB
- bool "256MB"
-config K8M890_VIDEO_MB_CMOS
- bool "Use CMOS option"
-
-endchoice
-
-config VIDEO_MB
- int
- default 32 if K8M890_VIDEO_MB_32MB
- default 64 if K8M890_VIDEO_MB_64MB
- default 128 if K8M890_VIDEO_MB_128MB
- default 256 if K8M890_VIDEO_MB_256MB
- default -1 if K8M890_VIDEO_MB_CMOS
- depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
-
-endif # SOUTHBRIDGE_K8T890
diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc
deleted file mode 100644
index ed6d3edc78..0000000000
--- a/src/southbridge/via/k8t890/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-ifeq ($(CONFIG_SOUTHBRIDGE_VIA_K8T890),y)
-
-ramstage-y += ctrl.c
-ramstage-y += dram.c
-ramstage-y += bridge.c
-ramstage-y += host.c
-ramstage-y += host_ctrl.c
-ramstage-y += pcie.c
-ramstage-y += traf_ctrl.c
-ramstage-y += error.c
-ramstage-y += chrome.c
-
-bootblock-y += romstrap.ld
-bootblock-y += romstrap.S
-
-endif
diff --git a/src/southbridge/via/k8t890/acpi/sleepstates.asl b/src/southbridge/via/k8t890/acpi/sleepstates.asl
deleted file mode 100644
index 487055548c..0000000000
--- a/src/southbridge/via/k8t890/acpi/sleepstates.asl
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
-Name (SSFG, 0x04)
-#else
-Name (SSFG, 0x00)
-#endif
-
-/* Supported sleep states: */
-Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
-
-If (And(SSFG, 0x04)) {
- Name(\_S3, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
-}
-
-Name(\_S5, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S5) - Soft Off */
diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c
deleted file mode 100644
index f7ccd75667..0000000000
--- a/src/southbridge/via/k8t890/bridge.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include "k8x8xx.h"
-
-static void bridge_enable(struct device *dev)
-{
- u8 tmp;
- printk(BIOS_DEBUG, "B188 device dump\n");
-
- /* VIA recommends this, sorry no known info. */
-
- writeback(dev, 0x40, 0x91);
- writeback(dev, 0x41, 0x40);
- writeback(dev, 0x43, 0x44);
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
- writeback(dev, 0x42, 0x80);
- writeback(dev, 0x44, 0x35);
-#else
- writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet
- * says it is reserved
- */
-#endif
- writeback(dev, 0x45, 0x3a);
- writeback(dev, 0x46, 0x88); /* PCI ID lo */
- writeback(dev, 0x47, 0xb1); /* PCI ID hi */
-
- /* Bridge control, K8M890 bit 3 should be set to enable VGA on AGP
- * (Forward VGA compatible memory and I/O cycles )
- */
-
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
- writeback(dev, 0x3e, 0x0a);
-#else
- writeback(dev, 0x3e, 0x16);
-#endif
- dump_south(dev);
-
- /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */
- tmp = pci_read_config8(dev, PCI_COMMAND);
- tmp &= ~0x3;
- pci_write_config8(dev, PCI_COMMAND, tmp);
-
-}
-
-static const struct device_operations bridge_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .enable = bridge_enable,
- .scan_bus = pci_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = 0,
-};
-
-/*
- * K8T890 and K8T800 both use device B188 as the bridge, so no need to
- * add a separate driver
- */
-static const struct pci_driver northbridge_driver_890 __pci_driver = {
- .ops = &bridge_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8T890CE_BR,
-};
diff --git a/src/southbridge/via/k8t890/chrome.c b/src/southbridge/via/k8t890/chrome.c
deleted file mode 100644
index 5b6d6d2e73..0000000000
--- a/src/southbridge/via/k8t890/chrome.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h> /* for memset */
-#include "k8x8xx.h"
-
-#include <pc80/vga_io.h>
-#include <pc80/vga.h>
-#include <arch/io.h>
-
-/*
- *
- */
-static void
-chrome_vga_init(struct device *dev)
-{
- vga_sr_write(0x10, 0x01); /* unlock extended regs */
-
- vga_sr_mask(0x1A, 0x02, 0x02); /* enable mmio */
-
- vga_sr_mask(0x1A, 0x40, 0x40); /* Software Reset */
-
- vga_cr_mask(0x6A, 0x00, 0xC8); /* Disable CRTC2 & Simultaneous */
-
- /* Make sure that non of the primary VGA overflow registers are set */
- vga_cr_write(0x33, 0x00);
- vga_cr_write(0x35, 0x00);
- vga_cr_mask(0x11, 0x00, 0x30);
-
- vga_sr_mask(0x16, 0x00, 0x40); /* Wire CRT to CRTC1 */
- vga_cr_mask(0x36, 0x00, 0x30); /* Power on CRT */
-
- /* Disable Extended Display Mode */
- vga_sr_mask(0x15, 0x00, 0x02);
-
- /* Disable Wrap-around */
- vga_sr_mask(0x15, 0x00, 0x20);
-
- /* Disable Extended Mode memory access */
- vga_sr_mask(0x1A, 0x00, 0x08);
-
- /* Make sure that we only touch CRTC1s DAC */
- vga_sr_mask(0x1A, 0x00, 0x01);
-
- /* Set up power to the clocks/crtcs */
- vga_sr_mask(0x19, 0x7F, 0x7F); /* enable clock gating for all. */
- vga_sr_mask(0x1B, 0xC0, 0xC0); /* secondary clock according to pm */
- vga_sr_mask(0x1B, 0x20, 0x30); /* primary clock is always on */
-
- /* set everything according to PM/Engine idle state except pci dma */
- vga_sr_write(0x2D, 0xFF); /* Power management control 1 */
- vga_sr_write(0x2E, 0xFB); /* Power management control 2 */
- vga_sr_write(0x3F, 0xFF); /* Power management control 3 */
-
- /* now set up the engine clock. */
- vga_sr_write(0x47, 0xB8);
- vga_sr_write(0x48, 0x08);
- vga_sr_write(0x49, 0x03);
-
- /* trigger engine clock setting */
- vga_sr_mask(0x40, 0x01, 0x01);
- vga_sr_mask(0x40, 0, 0x01);
-
- vga_cr_mask(0x30, 0x04, 0x04); /* Enable PowerNow in primary path */
- vga_cr_mask(0x36, 0x01, 0x01); /* Enable PCI Power Management */
-
- /* Power now indicators... */
- vga_cr_write(0x41, 0xB9);
- vga_cr_write(0x42, 0xB4);
- /* could these be the CRTC2 power now indicators? */
- vga_cr_write(0x9D, 0x80); /* Power Now Ending position enable */
- vga_cr_write(0x9E, 0xB4); /* Power Now Control 3 */
-
- /* primary fifo setting */
- vga_sr_mask(0x16, 0x28, 0xBF); /* pthreshold: 160 */
- vga_sr_write(0x17, 0x60); /* max depth: 194 */
- vga_sr_mask(0x18, 0x0E, 0xBF); /* high priority threshold: 56 */
- vga_sr_write(0x1C, 0x54); /* Fetch count */
-
- vga_sr_write(0x20, 0x40); /* display queue typical arbiter control 0 */
- vga_sr_write(0x21, 0x40); /* display queue typical arbiter control 1 */
- vga_sr_mask(0x22, 0x14, 0x1F); /* display queue expire number */
-
- /* Typical Arbiter Control */
- vga_sr_mask(0x41, 0x40, 0xF0); /* Request threshold */
- vga_sr_mask(0x42, 0x20, 0x20); /* Support Fetch Cycle with Length 2 */
-
- vga_sr_write(0x50, 0x1F); /* AGP Control Register */
- vga_sr_write(0x51, 0xF5); /* AGP FIFO Control 1 */
-
- vga_cr_mask(0x33, 0x08, 0x08); /* Enable Prefetch Mode */
-}
-
-/*
- *
- */
-static void
-chrome_init(struct device *dev)
-{
- uint32_t fb_size, fb_address;
-
- fb_size = k8m890_host_fb_size_get();
- if (!fb_size) {
- printk(BIOS_WARNING, "Chrome: Device has not been initialised in the"
- " ramcontroller!\n");
- return;
- }
-
- fb_address = pci_read_config32(dev, 0x10);
- fb_address &= ~0x0F;
- if (!fb_address) {
- printk(BIOS_WARNING, "Chrome: No FB BAR assigned!\n");
- return;
- }
-
- printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n",
- fb_size, fb_address);
-
- //k8m890_host_fb_direct_set(fb_address);
-
- if (IS_ENABLED(SOUTHBRIDGE_VIA_K8M890_VGA_EN)) {
- /* Now set up the VGA console */
- vga_io_init(); /* Enable full IO access */
-
- chrome_vga_init(dev);
-
- vga_textmode_init();
-
- printk(BIOS_INFO, "Chrome VGA Textmode initialized.\n");
-
- /* if we don't have console, at least print something... */
- vga_line_write(0, "Chrome VGA Textmode initialized.");
- }
-}
-
-static struct device_operations
-chrome_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = chrome_init,
- .scan_bus = 0,
- .enable = 0,
-};
-
-static const struct pci_driver unichrome_driver_800 __pci_driver = {
- .ops = &chrome_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8M800_CHROME,
-};
-
-static const struct pci_driver unichrome_driver_890 __pci_driver = {
- .ops = &chrome_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8M890_CHROME,
-};
diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c
deleted file mode 100644
index 61fa28ed19..0000000000
--- a/src/southbridge/via/k8t890/ctrl.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include "k8x8xx.h"
-
-void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs)
-{
- msr_t msr;
-
- regs->rom_shadow_ctrl_pg_c = 0xff;
- regs->rom_shadow_ctrl_pg_d = 0xff;
- regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff;
- regs->rom_shadow_ctrl_pg_f_memhole = 0x30;
- regs->smm_apic_decoding = 0x19;
- msr = rdmsr(TOP_MEM);
- regs->shadow_mem_ctrl = msr.lo >> 24;
- regs->low_top_address = msr.lo >> 16;
-}
-
-/* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate
- * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1)
- */
-
-void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb)
-{
- u8 regm3;
- struct k8x8xx_vt8237_mirrored_regs mregs;
-
- pci_write_config8(dev, 0x70, 0xc2);
-
- /* PCI Control */
-#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
- pci_write_config8(dev, 0x72, 0xee);
-#endif
- pci_write_config8(dev, 0x73, 0x01);
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
- pci_write_config8(dev, 0x74, 0x64);
- pci_write_config8(dev, 0x75, 0x3f);
-#else
- pci_write_config8(dev, 0x74, 0x24);
- pci_write_config8(dev, 0x75, 0x0f);
-#endif
- pci_write_config8(dev, 0x76, 0x50);
-#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
- pci_write_config8(dev, 0x77, 0x08);
-#endif
- pci_write_config8(dev, 0x78, 0x01);
- /* APIC on HT */
- pci_write_config8(dev, 0x7c, 0x7f);
- pci_write_config8(dev, 0x7f, 0x02);
-
- k8x8xx_vt8237_mirrored_regs_fill(&mregs);
-
- pci_write_config8(dev, 0x57, mregs.shadow_mem_ctrl); /* Shadow mem CTRL */
- pci_write_config8(dev, 0x61, mregs.rom_shadow_ctrl_pg_c); /* Shadow page C */
- pci_write_config8(dev, 0x62, mregs.rom_shadow_ctrl_pg_d); /* Shadow page D */
- pci_write_config8(dev, 0xe6, mregs.smm_apic_decoding); /* SMM and APIC decoding */
-
- regm3 = mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding; /* Shadow page E */
-
- /*
- * All access bits for 0xE0000-0xEFFFF encode as just 2 bits!
- * So the NB reg is quite inconsistent, we expect there only 0xff or 0x00,
- * and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64!
- */
- if (regm3 == 0xff)
- regm3 = 0xc0;
- else
- regm3 = 0x0;
-
- /* Shadow page F + memhole copy */
- pci_write_config8(dev, 0x63, regm3 | (mregs.rom_shadow_ctrl_pg_f_memhole & 0x3F));
-
-}
-
-
-
-/**
- * Setup the V-Link for VT8237R, 8X mode.
- *
- * For K8T890CF VIA recommends what is in VIA column, AW is award 8X:
- *
- * REG DEF AW VIA-8X VIA-4X
- * -----------------------------
- * NB V-Link Manual Driving Control strobe 0xb5 0x46 0x46 0x88 0x88
- * NB V-Link Manual Driving Control - Data 0xb6 0x46 0x46 0x88 0x88
- * NB V-Link Receiving Strobe Delay 0xb7 0x02 0x02 0x61 0x01
- * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4 0x10 0x10 0x11 0x11
- * SB V-Link Strobe Drive Control 0xb9 0x00 0xa5 0x98 0x98
- * SB V-Link Data drive Control???? 0xba 0x00 0xbb 0x77 0x77
- * SB V-Link Receive Strobe Delay???? 0xbb 0x04 0x11 0x11 0x11
- * SB V-Link Compensation Control bit0 (use b9) 0xb8 0x00 0x01 0x01 0x01
- * V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03
- * V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03
- */
-
-static void vt8237r_vlink_init(struct device *dev)
-{
- u8 reg;
-
- /*
- * This init code is valid only for the VT8237R! For different
- * southbridges (e.g. VT8237A, VT8237S, VT8237 (without plus R)
- * and VT8251) a different init code is required.
- */
-
- pci_write_config8(dev, 0xb5, 0x88);
- pci_write_config8(dev, 0xb6, 0x88);
- pci_write_config8(dev, 0xb7, 0x61);
-
- reg = pci_read_config8(dev, 0xb4);
- reg |= 0x11;
- pci_write_config8(dev, 0xb4, reg);
-
- pci_write_config8(dev, 0xb9, 0x98);
- pci_write_config8(dev, 0xba, 0x77);
- pci_write_config8(dev, 0xbb, 0x11);
-
- reg = pci_read_config8(dev, 0xb8);
- reg |= 0x1;
- pci_write_config8(dev, 0xb8, reg);
-
- pci_write_config8(dev, 0xb0, 0x06);
- pci_write_config8(dev, 0xb1, 0x01);
-
- /* Program V-link 8X 16bit full duplex, parity enabled. */
- pci_write_config8(dev, 0x48, 0xa3);
-}
-
-static void ctrl_init(struct device *dev)
-{
-
- printk(BIOS_DEBUG, "K8x8xx: Initializing V-Link to VT8237R sb: ");
- /* TODO: Fix some ordering issue for V-link set Rx77[6] and PCI1_Rx4F[0]
- should to 1 */
-
- /* C2P Read ACK Return Priority */
- /* PCI CFG Address bits[27:24] are used as extended register address
- bit[11:8] */
-
-#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
- pci_write_config8(dev, 0x47, 0x30);
-#endif
-
- /* VT8237R specific configuration other SB are done in their own directories */
-
- struct device *devsb = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC,
- 0);
- if (devsb) {
- vt8237r_vlink_init(dev);
- k8x8xx_vt8237r_cfg(dev, devsb);
- } else {
- printk(BIOS_DEBUG, "VT8237R LPC not found !\n");
- return;
- }
- printk(BIOS_DEBUG, " Done\n");
- printk(BIOS_DEBUG, " VIA_X_7 device dump:\n");
- dump_south(dev);
-
-}
-
-static struct pci_operations lops_pci = {
- .set_subsystem = pci_dev_set_subsystem,
-};
-
-static const struct device_operations ctrl_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = ctrl_init,
- .ops_pci = &lops_pci,
-};
-
-static const unsigned short ctrl_ids[] = {
- PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR,
- PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR,
- PCI_DEVICE_ID_VIA_K8T890CE_7,
- PCI_DEVICE_ID_VIA_K8T890CF_7,
- PCI_DEVICE_ID_VIA_K8M890CE_7,
- 0
-};
-
-static const struct pci_driver northbridge_driver_t800 __pci_driver = {
- .ops = &ctrl_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .devices= ctrl_ids,
-};
diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c
deleted file mode 100644
index 1f126ccaab..0000000000
--- a/src/southbridge/via/k8t890/dram.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <pc80/mc146818rtc.h>
-#include <lib.h>
-#include "k8x8xx.h"
-
-static void dram_enable(struct device *dev)
-{
- u16 reg;
- struct k8x8xx_vt8237_mirrored_regs mregs;
-
- k8x8xx_vt8237_mirrored_regs_fill(&mregs);
- /*
- * Enable Lowest Interrupt arbitration for APIC, enable NB APIC
- * decoding, MSI support, no SMRAM, compatible SMM.
- */
- pci_write_config8(dev, 0x86, mregs.smm_apic_decoding);
-
- /*
- * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if
- * memory is doing K8 the DMA from SB will fail if we have it wrong,
- * AND even we have it here, we must later copy it to SB to make it work :/
- */
-
- /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for
- * C0000-C3FFF etc.
- */
- pci_write_config8(dev, 0x80, mregs.rom_shadow_ctrl_pg_c);
- /* For page D0000-DFFFF */
- pci_write_config8(dev, 0x81, mregs.rom_shadow_ctrl_pg_d);
- /* For page E0000-EFFFF */
- pci_write_config8(dev, 0x82, mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding);
- pci_write_config8(dev, 0x83, mregs.rom_shadow_ctrl_pg_f_memhole);
-
- reg = pci_read_config16(dev, 0x84);
- reg &= 0xf;
- pci_write_config16(dev, 0x84, mregs.low_top_address | reg);
-
- reg = pci_read_config16(dev, 0x88);
- reg &= 0xf800;
-
- /* The Address Next to the Last Valid DRAM Address */
- pci_write_config16(dev, 0x88, reg | mregs.shadow_mem_ctrl);
-
- printk(BIOS_DEBUG, " VIA_X_3 device dump:\n");
- dump_south(dev);
-
-}
-
-static void dram_enable_k8m890(struct device *dev)
-{
-#if IS_ENABLED(CONFIG_GFXUMA)
- msr_t msr;
- int ret;
- unsigned int fbbits;
-
- /* use CMOS */
- if (CONFIG_VIDEO_MB == -1) {
- ret = get_option(&fbbits, "videoram_size");
- if (ret) {
- printk(BIOS_WARNING, "Failed to get videoram size (error %d), using default.\n", ret);
- fbbits = 5;
- }
-
- if ((fbbits < 1) || (fbbits > 7)) {
- printk(BIOS_WARNING, "Invalid videoram size (%d), using default.\n",
- 4 << fbbits);
- fbbits = 5;
- }
- uma_memory_size = 4 << (fbbits + 20);
- } else {
- uma_memory_size = (CONFIG_VIDEO_MB << 20);
- }
-
- msr = rdmsr(TOP_MEM);
- uma_memory_base = msr.lo - uma_memory_size;
- printk(BIOS_INFO, "K8M890: UMA base is %llx size is %u (MB)\n", uma_memory_base,
- (u32) (uma_memory_size / 1024 / 1024));
- /* enable VGA, so the bridges gets VGA_EN and resources are set */
- pci_write_config8(dev, 0xa1, 0x80);
-#endif
- dram_enable(dev);
-}
-
-int
-k8m890_host_fb_size_get(void)
-{
- struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_K8M800_DRAM, 0);
- if (!dev) dev = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
- unsigned char tmp;
-
- tmp = pci_read_config8(dev, 0xA1);
- tmp >>= 4;
- if (tmp & 0x08)
- return 4 << (tmp & 7);
- else
- return 0;
-}
-
-static void dram_init_fb(struct device *dev)
-{
-#if IS_ENABLED(CONFIG_GFXUMA)
- /* Important bits:
- * Enable the internal GFX bit 7 of reg 0xa1 plus in same reg:
- * bits 6:4 X fbuffer size will be 2^(X+2) or 100 = 64MB, 101 = 128MB
- * bits 3:0 BASE [31:28]
- * reg 0xa0 bits 7:1 BASE [27:21] bit0 enable CPU access
- */
- unsigned int fbbits = 0;
- u8 tmp;
-
- fbbits = ((log2(uma_memory_size >> 20) - 2) << 4);
- printk(BIOS_INFO, "K8M890: Using a %dMB framebuffer.\n", (unsigned int) (uma_memory_size >> 20));
-
- /* Step 1: enable UMA but no FB */
- pci_write_config8(dev, 0xa1, 0x80);
-
- /* Step 2: enough is just the FB size, the CPU accessible address is not needed */
- tmp = fbbits | 0x80;
- pci_write_config8(dev, 0xa1, tmp);
-
- /* TODO K8 needs some UMA fine tuning too maybe call some generic routine here? */
-#endif
-}
-
-static struct pci_operations lops_pci = {
- .set_subsystem = pci_dev_set_subsystem,
-};
-
-static const struct device_operations dram_ops_t = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .enable = dram_enable,
- .ops_pci = &lops_pci,
-};
-
-static const struct device_operations dram_ops_m = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .enable = dram_enable_k8m890,
- .init = dram_init_fb,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver northbridge_driver_t800 __pci_driver = {
- .ops = &dram_ops_t,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8T800_DRAM,
-};
-
-static const struct pci_driver northbridge_driver_m800 __pci_driver = {
- .ops = &dram_ops_m,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8M800_DRAM,
-};
-
-static const struct pci_driver northbridge_driver_t890 __pci_driver = {
- .ops = &dram_ops_t,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8T890CE_3,
-};
-
-static const struct pci_driver northbridge_driver_t890cf __pci_driver = {
- .ops = &dram_ops_t,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8T890CF_3,
-};
-
-static const struct pci_driver northbridge_driver_m890 __pci_driver = {
- .ops = &dram_ops_m,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8M890CE_3,
-};
diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c
deleted file mode 100644
index 64f0425c25..0000000000
--- a/src/southbridge/via/k8t890/early_car.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * Seems the link and width of HT link needs to be setup too, you need to
- * generate PCI reset or LDTSTOP to apply.
- */
-
-#include <stdlib.h>
-#include <cbmem.h>
-#include <arch/io.h>
-#include <arch/acpi.h>
-#include "k8x8xx.h"
-
-/* The 256 bytes of NVRAM for S3 storage, 256B aligned */
-#define K8T890_NVRAM_IO_BASE 0xf00
-#define K8T890_MULTIPLE_FN_EN 0x4f
-
-/* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */
-static u8 ldtreg[3] = {0x86, 0xa6, 0xc6};
-
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
-#define K8X8XX_HT_CFG_BASE 0xc0
-#else
-#define K8X8XX_HT_CFG_BASE 0x60
-#endif
-
-/* This functions sets KT890 link frequency and width to same values as
- * it has been setup on K8 side, by AMD NB init.
- * This will not work for K8T800_OLD, which has a slightly different
- * register arrangement (device 3188)
- */
-
-u8 k8t890_early_setup_ht(void)
-{
- u8 awidth, afreq, cldtfreq;
- u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width;
- u16 vldtcaps;
-
-#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
- u8 reg;
-
- /* hack, enable NVRAM in chipset */
- pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01);
-
- /*
- * NVRAM I/O base at K8T890_NVRAM_IO_BASE
- */
-
- pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
- reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1);
- reg |= 0x1;
- pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg);
-#endif
-
- /* check if connected non coherent, initcomplete (find the SB on K8 side) */
- ldtnr = 0;
- if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0x98)) {
- ldtnr = 0;
- } else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xb8)) {
- ldtnr = 1;
- } else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xd8)) {
- ldtnr = 2;
- }
-
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800)
- printk(BIOS_DEBUG, "K8M800 found at LDT ");
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800)
- printk(BIOS_DEBUG, "K8T800 found at LDT ");
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
- printk(BIOS_DEBUG, "K8T800_OLD found at LDT ");
- pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00);
- pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50);
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800PRO)
- printk(BIOS_DEBUG, "K8T800 Pro found at LDT ");
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890)
- printk(BIOS_DEBUG, "K8M890 found at LDT ");
- /* K8M890 fix HT delay */
- pci_write_config8(PCI_DEV(0, 0x0, 2), 0xab, 0x22);
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890)
- printk(BIOS_DEBUG, "K8T890 found at LDT ");
-#endif
- printk(BIOS_DEBUG, "%02x", ldtnr);
-
- /* get the maximum widths for both sides */
- cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7;
- cldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) >> 4) & 0x7;
- vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) & 0x7;
- vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) >> 4) & 0x7;
-
- width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in);
- printk(BIOS_DEBUG, " Agreed on width: %02x", width);
-
- awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7);
-
- /* Update the desired HT LNK to match AMD NB max from VIA NB is 0x1 */
- width = (width == 0x01) ? 0x11 : 0x00;
-
- pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7, width);
-
- /* Get programmed HT freq at base 0x89 */
- cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf;
- printk(BIOS_DEBUG, " CPU programmed to HT freq: %02x", cldtfreq);
-
- vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), K8X8XX_HT_CFG_BASE + 0xe);
- printk(BIOS_DEBUG, " VIA HT caps: %04x", vldtcaps);
-
- if (!(vldtcaps & (1 << cldtfreq ))) {
- die("Chipset does not support desired HT frequency\n");
- }
-
- afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd);
- pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd, cldtfreq);
- printk(BIOS_DEBUG, "\n");
-
- /* no reset needed */
- if ((width == awidth) && (afreq == cldtfreq)) {
- return 0;
- }
-
- return 1;
-}
-
-int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
-{
-
- printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
- switch (size) {
- case 1:
- outb((dword & 0xff), K8T890_NVRAM_IO_BASE+nvram_pos);
- nvram_pos +=1;
- break;
- case 2:
- outw((dword & 0xffff), K8T890_NVRAM_IO_BASE+nvram_pos);
- nvram_pos +=2;
- break;
- default:
- outl(dword, K8T890_NVRAM_IO_BASE+nvram_pos);
- nvram_pos +=4;
- break;
- }
- return nvram_pos;
-}
-
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
-{
- switch (size) {
- case 1:
- *old_dword &= ~0xff;
- *old_dword |= inb(K8T890_NVRAM_IO_BASE+nvram_pos);
- nvram_pos +=1;
- break;
- case 2:
- *old_dword &= ~0xffff;
- *old_dword |= inw(K8T890_NVRAM_IO_BASE+nvram_pos);
- nvram_pos +=2;
- break;
- default:
- *old_dword = inl(K8T890_NVRAM_IO_BASE+nvram_pos);
- nvram_pos +=4;
- break;
- }
- printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size);
- return nvram_pos;
-}
-
-uintptr_t restore_top_of_low_cacheable(void)
-{
- if (acpi_get_sleep_type() != 3)
- return 0;
- return inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM);
-}
diff --git a/src/southbridge/via/k8t890/error.c b/src/southbridge/via/k8t890/error.c
deleted file mode 100644
index ad9b0d0ed9..0000000000
--- a/src/southbridge/via/k8t890/error.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include "k8x8xx.h"
-
-static void error_enable(struct device *dev)
-{
- printk(BIOS_DEBUG, " K8x8xx: Enabling NB error reporting: ");
- /*
- * bit0 - Enable V-link parity error reporting in 0x50 bit0 (RWC)
- * bit6 - Parity Error/SERR# Report Through V-Link to SB
- * bit7 - Parity Error/SERR# Report Through NMI
- */
- pci_write_config8(dev, 0x58, 0x81);
-
- printk(BIOS_DEBUG, "Done\n");
- /* TODO: enable AGP errors reporting on K8M890 */
-
- printk(BIOS_DEBUG, " VIA_X_1 device dump:\n");
- dump_south(dev);
-}
-
-static struct pci_operations lops_pci = {
- .set_subsystem = pci_dev_set_subsystem,
-};
-
-static const struct device_operations error_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .enable = error_enable,
- .ops_pci = &lops_pci,
-};
-
-static const unsigned short error_ids[] = {
- PCI_DEVICE_ID_VIA_K8T800_ERR,
- PCI_DEVICE_ID_VIA_K8M800_ERR,
- PCI_DEVICE_ID_VIA_K8T890CE_1,
- PCI_DEVICE_ID_VIA_K8T890CF_1,
- PCI_DEVICE_ID_VIA_K8M890CE_1,
- 0
-};
-
-static const struct pci_driver northbridge_driver_t800 __pci_driver = {
- .ops = &error_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .devices= error_ids,
-};
diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c
deleted file mode 100644
index 2155594cd0..0000000000
--- a/src/southbridge/via/k8t890/host.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include "k8x8xx.h"
-
-static void host_old_enable(struct device *dev)
-{
- int agp3;
-
- /* some HT tweaking */
- pci_write_config8(dev, 0x50, 0x03);
- pci_write_config8(dev, 0x55, 0x2c);
-
- /* AGP setup */
- pci_write_config8(dev, 0xac, 0x06);
- pci_write_config8(dev, 0xad, 0x08);
- pci_write_config8(dev, 0xfd, 0x02);
- pci_write_config8(dev, 0x85, 0xb0);
- pci_write_config8(dev, 0x87, 0x07);
- pci_write_config8(dev, 0xfd, 0x06); // this is required for the following write to work
- pci_write_config8(dev, 0xaf, 0x88);
- pci_write_config8(dev, 0xfd, 0x04); // select AGP 3.0
- agp3 = pci_read_config8(dev, 0x84) & 0x08;
- pci_write_config8(dev, 0xb1, agp3 ? 0x00 : 0x9B);
- pci_write_config8(dev, 0xb3, agp3 ? 0x00 : 0x9B);
- pci_write_config8(dev, 0xb0, 0x40);
- pci_write_config8(dev, 0xb2, 0x11);
- pci_write_config8(dev, 0xed, 0x40);
-}
-
-static void host_old_init(struct device *dev)
-{
- k8x8xx_vt8237r_cfg(dev, NULL);
-}
-
-static void host_enable(struct device *dev)
-{
- /* Multiple function control */
- pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
-
- printk(BIOS_DEBUG, " VIA_X_0 device dump:\n");
- dump_south(dev);
-}
-
-
-static void host_init(struct device *dev)
-{
- u8 reg;
-
- /* AGP Capability Header Control */
- reg = pci_read_config8(dev, 0x4d);
- reg |= 0x20; /* GART access enabled by either D0F0 Rx90[8] or D1F0 Rx90[8] */
- pci_write_config8(dev, 0x4d, reg);
-
- /* GD Output Stagger Delay */
- reg = pci_read_config8(dev, 0x42);
- reg |= 0x10; /* AD[31:16] with 1ns */
- pci_write_config8(dev, 0x42, reg);
-
- /* AGP Control */
- reg = pci_read_config8(dev, 0xbc);
- reg |= 0x20; /* AGP Read Snoop DRAM Post-Write Buffer */
- pci_write_config8(dev, 0xbc, reg);
-
-}
-
-static const struct device_operations host_ops_old = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .enable = host_old_enable,
- .init = host_old_init,
- .ops_pci = 0,
-};
-
-static struct pci_operations lops_pci = {
- .set_subsystem = pci_dev_set_subsystem,
-};
-
-static const struct device_operations host_ops_t = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .enable = host_enable,
- .ops_pci = &lops_pci,
-};
-
-static const struct device_operations host_ops_m = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .enable = host_enable,
- .init = host_init,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver northbridge_driver_t800_old __pci_driver = {
- .ops = &host_ops_old,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8T800_AGP,
-};
-
-static const struct pci_driver northbridge_driver_t800 __pci_driver = {
- .ops = &host_ops_t,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8T800_HT_AGP_CTR,
-};
-
-static const struct pci_driver northbridge_driver_m800 __pci_driver = {
- .ops = &host_ops_m,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8M800_HT_AGP_CTR,
-};
-
-static const struct pci_driver northbridge_driver_t890 __pci_driver = {
- .ops = &host_ops_t,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8T890CE_0,
-};
-
-static const struct pci_driver northbridge_driver_t890cf __pci_driver = {
- .ops = &host_ops_t,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8T890CF_0,
-};
-
-static const struct pci_driver northbridge_driver_m890 __pci_driver = {
- .ops = &host_ops_m,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8M890CE_0,
-};
diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c
deleted file mode 100644
index 3e7a2c74b0..0000000000
--- a/src/southbridge/via/k8t890/host_ctrl.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include <cbmem.h>
-#include <arch/io.h>
-#include "k8x8xx.h"
-
-/* this may be later merged */
-
-/* This fine tunes the HT link settings, which were loaded by ROM strap. */
-static void host_ctrl_enable_k8t8xx(struct device *dev)
-{
- /*
- * Bit 4 is reserved but set by AW. Set PCI to HT outstanding
- * requests to 3.
- */
- pci_write_config8(dev, 0xa0, 0x13);
-
- /*
- * NVRAM I/O base at K8T890_NVRAM_IO_BASE
- * Some bits are set and reserved.
- */
- pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
-
- /* enable NB NVRAM and enable non-posted PCI writes. */
- pci_write_config8(dev, 0xa1, 0x8f);
- /* Arbitration control, some bits are reserved. */
- pci_write_config8(dev, 0xa5, 0x3c);
-
- /* Arbitration control 2 */
- pci_write_config8(dev, 0xa6, 0x80);
-
- /* this will be possibly removed, when I figure out
- * if the ROM SIP is good, second reason is that the
- * unknown bits are AGP related, which are dummy on K8T890
- */
-
- writeback(dev, 0xa0, 0x13); /* Bit4 is reserved! */
- writeback(dev, 0xa1, 0x8e); /* Some bits are reserved. */
- writeback(dev, 0xa2, 0x0e); /* I/O NVRAM base 0xe00-0xeff disabled. */
- writeback(dev, 0xa3, 0x31);
- writeback(dev, 0xa4, 0x30);
-
- writeback(dev, 0xa5, 0x3c); /* Some bits reserved. */
- writeback(dev, 0xa6, 0x80); /* Some bits reserved. */
- writeback(dev, 0xa7, 0x86); /* Some bits reserved. */
- writeback(dev, 0xa8, 0x7f); /* Some bits reserved. */
- writeback(dev, 0xa9, 0xcf); /* Some bits reserved. */
- writeback(dev, 0xaa, 0x44);
- writeback(dev, 0xab, 0x22);
- writeback(dev, 0xac, 0x35); /* Maybe bit0 is read-only? */
-
- writeback(dev, 0xae, 0x22);
- writeback(dev, 0xaf, 0x40);
- /* b0 is missing. */
- writeback(dev, 0xb1, 0x13);
- writeback(dev, 0xb4, 0x02); /* Some bits are reserved. */
- writeback(dev, 0xc0, 0x20);
- writeback(dev, 0xc1, 0xaa);
- writeback(dev, 0xc2, 0xaa);
- writeback(dev, 0xc3, 0x02);
- writeback(dev, 0xc4, 0x50);
- writeback(dev, 0xc5, 0x50);
-
- printk(BIOS_DEBUG, " VIA_X_2 device dump:\n");
- dump_south(dev);
-}
-
-/* This fine tunes the HT link settings, which were loaded by ROM strap. */
-static void host_ctrl_enable_k8m8xx(struct device *dev) {
-
- /*
- * Set PCI to HT outstanding requests to 03.
- * Bit 4 32 AGP ADS Read Outstanding Request Number
- */
- pci_write_config8(dev, 0xa0, 0x13);
-
- /*
- * NVRAM I/O base at K8T890_NVRAM_IO_BASE
- */
-
- pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
-
- /* Enable NVRAM and enable non-posted PCI writes. */
- pci_write_config8(dev, 0xa1, 0x8f);
-
- /* Arbitration control */
- pci_write_config8(dev, 0xa5, 0x3c);
-
- /* Arbitration control 2, Enable C2NOW delay to PSTATECTL */
- pci_write_config8(dev, 0xa6, 0x83);
-
-}
-
-void backup_top_of_low_cacheable(uintptr_t ramtop)
-{
- outl((u32) ramtop, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM);
-}
-
-static struct pci_operations lops_pci = {
- .set_subsystem = pci_dev_set_subsystem,
-};
-
-static const struct device_operations host_ctrl_ops_t = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .enable = host_ctrl_enable_k8t8xx,
- .ops_pci = &lops_pci,
-};
-
-static const struct device_operations host_ctrl_ops_m = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .enable = host_ctrl_enable_k8m8xx,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver northbridge_driver_t800 __pci_driver = {
- .ops = &host_ctrl_ops_t,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8T800_HOST_CTR,
-};
-
-static const struct pci_driver northbridge_driver_m800 __pci_driver = {
- .ops = &host_ctrl_ops_m,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8M800_HOST_CTR,
-};
-
-static const struct pci_driver northbridge_driver_t890 __pci_driver = {
- .ops = &host_ctrl_ops_t,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8T890CE_2,
-};
-
-static const struct pci_driver northbridge_driver_m890 __pci_driver = {
- .ops = &host_ctrl_ops_m,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8M890CE_2,
-};
diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h
deleted file mode 100644
index 8bb52db4c5..0000000000
--- a/src/southbridge/via/k8t890/k8t890.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SOUTHBRIDGE_VIA_K8T890_K8T890_H
-#define SOUTHBRIDGE_VIA_K8T890_K8T890_H
-
-/* Static resources for K8T890. */
-#define K8T890_APIC_ID 0x3
-
-/*
- * Please check the datasheet and traf_ctrl_enable before change!
- * It can't be changed to an arbitrary address.
- */
-#define K8T890_APIC_BASE 0xfecc0000
-
-/* The 256 bytes of NVRAM for S3 storage, 256B aligned */
-#define K8T890_NVRAM_IO_BASE 0xf00
-#define K8T890_NVRAM_TOP_OF_RAM 0xfc
-
-#define K8T890_MMCONFIG_MBAR 0x61
-#define K8T890_MULTIPLE_FN_EN 0x4f
-
-/* the FB size in MB (min is 8MB max is 512MB) */
-#define K8M890_FBSIZEMB 64
-
-#ifdef __PRE_RAM__
-u8 k8t890_early_setup_ht(void);
-int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
-#define k8x8xx_early_setup_ht() k8t890_early_setup_ht()
-#else
-#include <device/device.h>
-#if 0
-extern void writeback(struct device *dev, u16 where, u8 what);
-extern void dump_south(struct device *dev);
-#endif
-#endif
-
-#include <southbridge/via/vt8237r/vt8237r.h>
-
-int k8m890_host_fb_size_get(void);
-//void k8m890_host_fb_direct_set(uint32_t fb_address);
-
-#endif
diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h
deleted file mode 100644
index 4311ae8bcc..0000000000
--- a/src/southbridge/via/k8t890/k8x8xx.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H
-#define SOUTHBRIDGE_VIA_K8T890_K8X8XX_H
-
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#ifndef __PRE_RAM__
-#include <device/device.h>
-#endif
-#include "k8t890.h"
-
-#ifndef __PRE_RAM__
-struct k8x8xx_vt8237_mirrored_regs {
- u16 low_top_address;
- u8 rom_shadow_ctrl_pg_c,
- rom_shadow_ctrl_pg_d,
- rom_shadow_ctrl_pg_e_memhole_smi_decoding,
- rom_shadow_ctrl_pg_f_memhole,
- smm_apic_decoding,
- shadow_mem_ctrl;
-};
-
-void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs);
-void k8x8xx_vt8237r_cfg(struct device *, struct device *);
-#endif
-
-#endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */
diff --git a/src/southbridge/via/k8t890/pcie.c b/src/southbridge/via/k8t890/pcie.c
deleted file mode 100644
index d93fd17516..0000000000
--- a/src/southbridge/via/k8t890/pcie.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pciexp.h>
-#include <device/pci_ids.h>
-#include <delay.h>
-#include "k8t890.h"
-
-/*
- * Note:
- * The pcie bridges are similar to the VX800 ones documented at
- * http://linux.via.com.tw/
- */
-
-static void pcie_common_init(struct device *dev)
-{
- u8 reg;
- int i, up;
-
- /* Disable downstream read cycle retry,
- * otherwise the bus scan will hang if no device is plugged in. */
- reg = pci_read_config8(dev, 0xa3);
- pci_write_config8(dev, 0xa3, reg & ~0x01);
-
- /* Use PHY negotiation for lane config */
- reg = pci_read_config8(dev, 0xc1);
- pci_write_config8(dev, 0xc1, reg & ~0x1f);
-
- /* Award has 0xb, VIA recommends 0xd, default 0x8.
- * bit4: receive polarity change control
- * bits3:2: squelch window select 64~175mv
- * bit1: Number of non-idle bits detected before exiting idle state
- * 0: 10 bits, 1: 2 bits
- * bit0: Number of idle bits detected before entering idle state
- * 0: 10 bits, 1: 2 bits
- */
- pci_write_config8(dev, 0xe1, 0xb);
-
- /* Set replay timer limit. */
- pci_write_config8(dev, 0xb1, 0xf0);
-
- /* Enable link. */
- reg = pci_read_config8(dev, 0x50);
- pci_write_config8(dev, 0x50, reg & ~0x10);
-
- /* Wait up to 100ms for link to come up */
- up = 0;
- for (i = 0; i < 1000; i++) {
- if (pci_read_config16(dev, 0x52) & (1<<13)) {
- up = 1;
- break;
- }
- udelay(100);
- }
-
- printk(BIOS_SPEW, "%s PCIe link ", dev_path(dev));
- if (up)
- printk(BIOS_SPEW, "up after %d us\n", i*100);
- else
- printk(BIOS_SPEW, "timeout\n");
-
- dump_south(dev);
-}
-
-static void peg_init(struct device *dev)
-{
- u8 reg;
-
- printk(BIOS_DEBUG, "Configuring PCIe PEG\n");
- dump_south(dev);
-
- /* Disable link. */
- reg = pci_read_config8(dev, 0x50);
- pci_write_config8(dev, 0x50, reg | 0x10);
-
- /*
- * pci_write_config8(dev, 0xe2, 0x0);
- * pci_write_config8(dev, 0xe3, 0x92);
- */
-
- /* Bit0 = 1 SDP (Start DLLP) always at Lane0. */
- reg = pci_read_config8(dev, 0xb8);
- pci_write_config8(dev, 0xb8, reg | 0x1);
-
- /*
- * Downstream wait and Upstream Checking Malformed TLP through
- * "Byte Enable Rule" And "Over 4K Boundary Rule".
- */
- reg = pci_read_config8(dev, 0xa4);
- pci_write_config8(dev, 0xa4, reg | 0x30);
-
- pcie_common_init(dev);
-}
-
-static void pcie_init(struct device *dev)
-{
- u8 reg;
-
- printk(BIOS_DEBUG, "Configuring PCIe PEXs\n");
- dump_south(dev);
-
- /* Disable link. */
- reg = pci_read_config8(dev, 0x50);
- pci_write_config8(dev, 0x50, reg | 0x10);
-
- pcie_common_init(dev);
-}
-
-static const struct device_operations peg_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .enable = peg_init,
- .scan_bus = pciexp_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = 0,
-};
-
-static const struct device_operations pcie_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .enable = pcie_init,
- .scan_bus = pciexp_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = 0,
-};
-
-static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &peg_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8T890CE_PEG,
-};
-
-static const unsigned short pci_device_ids[] = {
- PCI_DEVICE_ID_VIA_K8T890CE_PEX0,
- PCI_DEVICE_ID_VIA_K8T890CE_PEX1,
- PCI_DEVICE_ID_VIA_K8T890CE_PEX2,
- PCI_DEVICE_ID_VIA_K8T890CE_PEX3,
- 0,
-};
-
-static const struct pci_driver pex_driver __pci_driver = {
- .ops = &pcie_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .devices = pci_device_ids,
-};
diff --git a/src/southbridge/via/k8t890/romstrap.S b/src/southbridge/via/k8t890/romstrap.S
deleted file mode 100644
index cb384e969d..0000000000
--- a/src/southbridge/via/k8t890/romstrap.S
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Tyan Computer
- * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer)
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This file constructs the ROM strap table for K8T890 and K8M890 */
-
-.section ".romstrap", "a", @progbits
-
-.globl __romstrap_start
-.globl __romstrap_end
-
-__romstrap_start:
-
-/*
- * Below are some Dev0 Func2 HT control registers values,
- * depending on strap pin, one of below lines is used.
- */
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800) || \
- IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800) || \
- IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
-
-tblpointer:
-.long 0x50220000, 0X619707C2
-.long 0x50220000, 0X619707C2
-.long 0x50220000, 0X619707C2
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890)
-
-tblpointer:
-.long 0x504400FF, 0x61970FC2 //;200M
-.long 0x504400FF, 0x61970FC2 //;400M
-.long 0x504400FF, 0x61970FC2 //;600M
-.long 0x504400FF, 0x61970FC2 //;800M
-.long 0x504400FF, 0x61970FC2 //;1000M
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-
-
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890)
-
-tblpointer:
-.long 0x504400AA, 0x61970FC2 //;200M
-.long 0x504400AA, 0x61970FC2 //;400M
-.long 0x504400AA, 0x61970FC2 //;600M
-.long 0x504400AA, 0x61970FC2 //;800M
-.long 0x504400AA, 0x61970FC2 //;1000M
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-.long 0x0
-
-#endif
-/*
- * The pointer to above table should be at 0xffffd,
- * the table itself MUST be aligned to 128B it seems!
- */
-.long tblpointer - 0xFFF00000
-
-__romstrap_end:
-
-.previous
diff --git a/src/southbridge/via/k8t890/romstrap.ld b/src/southbridge/via/k8t890/romstrap.ld
deleted file mode 100644
index ac568efacc..0000000000
--- a/src/southbridge/via/k8t890/romstrap.ld
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghai.lu@amd.com> for AMD)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Modified for K8T890 ROM strap by Rudolf Marek <r.marek@assembler.cz>. */
-
-SECTIONS {
- . = (0xffffffff - 0x2c) - (__romstrap_end - __romstrap_start) + 1;
- .romstrap (.): {
- KEEP(*(.romstrap))
- }
-}
diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c
deleted file mode 100644
index de26e225a5..0000000000
--- a/src/southbridge/via/k8t890/traf_ctrl.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <cpu/amd/powernow.h>
-#include <lib.h>
-#include "k8t890.h"
-
-static void mmconfig_set_resources(struct device *dev)
-{
- struct resource *resource;
- u8 reg;
-
- resource = find_resource(dev, K8T890_MMCONFIG_MBAR);
- if (resource) {
- report_resource_stored(dev, resource, "<mmconfig>");
-
- /* Remember this resource has been stored. */
- resource->flags |= IORESOURCE_STORED;
- pci_write_config8(dev, K8T890_MMCONFIG_MBAR,
- (resource->base >> 28));
- reg = pci_read_config8(dev, 0x60);
- reg |= 0x3;
- /* Enable MMCONFIG decoding. */
- pci_write_config8(dev, 0x60, reg);
- }
- pci_dev_set_resources(dev);
-}
-
-static void apic_mmconfig_read_resources(struct device *dev)
-{
- struct resource *res;
- pci_dev_read_resources(dev);
-
- res = new_resource(dev, 0x40);
- /* NB APIC fixed to this address. */
- res->base = K8T890_APIC_BASE;
- res->size = 256;
- res->limit = res->base + res->size - 1;
- res->align = 8;
- res->gran = 8;
- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
- IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-
- /* Add an MMCONFIG resource. */
- res = new_resource(dev, K8T890_MMCONFIG_MBAR);
- res->size = 256 * 1024 * 1024;
- res->align = log2(res->size);
- res->gran = log2(res->size);
- res->limit = 0xffffffff; /* 4G */
- res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE;
-}
-
-static void traf_ctrl_enable_generic(struct device *dev)
-{
- volatile u32 *apic;
- u32 data;
-
- /* no device2 redirect, enable just one device behind
- * bridge device 2 and device 3).
- */
- pci_write_config8(dev, 0x60, 0x08);
-
- /* Will enable MMCONFIG later. */
- pci_write_config8(dev, 0x64, 0x23);
- /* No extended RCRB Base Address. */
- pci_write_config8(dev, 0x62, 0x00);
-
- /* Offset80 ->95 bit 4 in 1 in Award. */
-
- /* Enable APIC, to K8T890_APIC_BASE. */
- pci_write_config8(dev, 0x41, 0x00);
- pci_write_config8(dev, 0x40, 0x8c);
- /* BT_INTR enable, APIC Nonshare Mode Enable. */
- pci_write_config8(dev, 0x42, 0x5);
-
- apic = (u32 *)K8T890_APIC_BASE;
-
- /* Set APIC to FSB transported messages. */
- apic[0] = 3;
- data = apic[4];
- apic[4] = (data & 0xFFFFFE) | 1;
-
- /* Set APIC ID. */
- apic[0] = 0;
- data = apic[4];
- apic[4] = (data & 0xF0FFFF) | (K8T890_APIC_ID << 24);
-}
-
-static void traf_ctrl_enable_k8m890(struct device *dev)
-{
- traf_ctrl_enable_generic(dev);
-}
-
-static void traf_ctrl_enable_k8t890(struct device *dev)
-{
- u8 reg;
-
- traf_ctrl_enable_generic(dev);
-
- /* Enable D3F1-D3F3 */
- reg = pci_read_config8(dev, 0x60);
- pci_write_config8(dev, 0x60, 0x80 | reg);
-}
-
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
-
-static void southbridge_acpi_fill_ssdt_generator(struct device *dev) {
- amd_generate_powernow(0, 0, 0);
- acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
-}
-
-#endif
-
-static const struct device_operations traf_ctrl_ops_m = {
- .read_resources = apic_mmconfig_read_resources,
- .set_resources = mmconfig_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .enable = traf_ctrl_enable_k8m890,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
- .write_acpi_tables = acpi_write_hpet,
- .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator,
-#endif
- .ops_pci = 0,
-};
-
-static const struct device_operations traf_ctrl_ops_t = {
- .read_resources = apic_mmconfig_read_resources,
- .set_resources = mmconfig_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .enable = traf_ctrl_enable_k8t890,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
- .write_acpi_tables = acpi_write_hpet,
-#endif
- .ops_pci = 0,
-};
-
-/* K8X800 chipsets have no APIC; no 800 PCI ids here */
-
-unsigned long acpi_fill_mcfg(unsigned long current)
-{
- struct device *dev;
- struct resource *res;
-
- dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0);
- if (!dev)
- dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_5, 0);
- if (!dev)
- dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_5, 0);
- if (!dev)
- return current;
-
- res = find_resource(dev, K8T890_MMCONFIG_MBAR);
- if (res) {
- current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)
- current, res->base, 0x0, 0x0, 0xff);
- }
- return current;
-}
-
-
-static const struct pci_driver northbridge_driver_t __pci_driver = {
- .ops = &traf_ctrl_ops_t,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8T890CE_5,
-};
-
-static const struct pci_driver northbridge_driver_tcf __pci_driver = {
- .ops = &traf_ctrl_ops_t,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8T890CF_5,
-};
-
-static const struct pci_driver northbridge_driver_m __pci_driver = {
- .ops = &traf_ctrl_ops_m,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8M890CE_5,
-};
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 46b1e237fd..998340f419 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -319,21 +319,11 @@ static void vt8237r_init(struct device *dev)
*/
pci_write_config8(dev, 0x48, 0x0c);
#else
-
- #if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800) || \
- IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
- /* It seems that when we pair with the K8T800, we need to disable
- * the A2 mask
- */
- pci_write_config8(dev, 0x48, 0x0c);
- #else
/*
* Set Read Pass Write Control Enable
* (force A2 from APIC FSB to low).
*/
pci_write_config8(dev, 0x48, 0x8c);
- #endif
-
#endif
southbridge_init_common(dev);