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authorKyösti Mälkki <kyosti.malkki@gmail.com>2015-01-09 23:48:47 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-01-10 13:53:51 +0100
commit78c5d584a087265e44b076647db19efd4db4a7bb (patch)
tree0f5e32c90cf0fb17db36d514baf6afc9c037d728 /src/southbridge/via
parent2320cbebc667ac6871d4d6c8b59fee27ba6e75e5 (diff)
downloadcoreboot-78c5d584a087265e44b076647db19efd4db4a7bb.tar.xz
ACPI: Add acpi_is_wakeup_s3() for romstage
This replaces acpi_is_wakeup_early(). Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8187 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge/via')
-rw-r--r--src/southbridge/via/k8t890/early_car.c4
-rw-r--r--src/southbridge/via/vt8237r/early_smbus.c4
-rw-r--r--src/southbridge/via/vt8237r/lpc.c10
3 files changed, 8 insertions, 10 deletions
diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c
index 7eba967a73..d41e0df422 100644
--- a/src/southbridge/via/k8t890/early_car.c
+++ b/src/southbridge/via/k8t890/early_car.c
@@ -180,11 +180,9 @@ static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
-#if CONFIG_HAVE_ACPI_RESUME
unsigned long get_top_of_ram(void)
{
- if (!acpi_is_wakeup_early())
+ if (acpi_get_sleep_type() != 3)
return 0;
return (unsigned long) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM);
}
-#endif
diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c
index bb06322849..b766bd74c8 100644
--- a/src/southbridge/via/vt8237r/early_smbus.c
+++ b/src/southbridge/via/vt8237r/early_smbus.c
@@ -330,8 +330,7 @@ void enable_rom_decode(void)
pci_write_config8(dev, 0x41, 0x7f);
}
-#if CONFIG_HAVE_ACPI_RESUME
-int acpi_is_wakeup_early(void)
+int acpi_get_sleep_type(void)
{
device_t dev;
u16 tmp;
@@ -354,7 +353,6 @@ int acpi_is_wakeup_early(void)
printk(BIOS_DEBUG, "%02x", tmp);
return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
}
-#endif
#if defined(__GNUC__)
void vt8237_early_spi_init(void)
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 92eaa39ac6..d3e3d324f6 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -244,10 +244,6 @@ static void setup_pm(device_t dev)
/* SCI is generated for RTC/pwrBtn/slpBtn. */
tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
-#if CONFIG_HAVE_ACPI_RESUME
- acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
- printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
-#endif
/* All SMI on, both IDE buses ON, PSON rising edge. */
outw(0x1, VT8237R_ACPI_IO_BASE + 0x2c);
@@ -258,6 +254,12 @@ static void setup_pm(device_t dev)
outw(tmp, VT8237R_ACPI_IO_BASE + 0x04);
}
+int acpi_get_sleep_type(void)
+{
+ u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
+ return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
+}
+
static void vt8237r_init(struct device *dev)
{
u8 enables;