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| author | Ronald G. Minnich <rminnich@gmail.com> | 2003-09-26 22:10:53 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2003-09-26 22:10:53 +0000 |
| commit | f3c17ca23409078b7f77e4b200aee0fd22d0cabc (patch) | |
| tree | 2d9993bfedee70bb2c6361082ca2bfa97f11d6c1 /src/southbridge/via | |
| parent | 42acd12cbc5a5fe6054cdd19de76cbe35d2aef9e (diff) | |
| download | coreboot-f3c17ca23409078b7f77e4b200aee0fd22d0cabc.tar.xz | |
via epia is putting out bytes!
ron
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via')
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_early_serial.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/src/southbridge/via/vt8231/vt8231_early_serial.c b/src/southbridge/via/vt8231/vt8231_early_serial.c index 168ee07377..ca7831df42 100644 --- a/src/southbridge/via/vt8231/vt8231_early_serial.c +++ b/src/southbridge/via/vt8231/vt8231_early_serial.c @@ -31,19 +31,24 @@ vt8231_writesioword(uint16_t reg, uint16_t val) { static void enable_vt8231_serial(void) { + unsigned long x; + uint8_t c; device_t dev; - - dev = pci_locate_device(PCI_ID(0x1106,0x3065), 0); + outb(6, 0x80); + dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); if (dev == PCI_DEV_INVALID) { + outb(7, 0x80); die("Serial controller not found\r\n"); } - /* first, you have to enable the superio and superio config. - put a 3 in devfn 38 reg 85 + put a 6 reg 80 */ - pci_write_config8(dev, 0x85, 3); + c = pci_read_config8(dev, 0x50); + c |= 6; + pci_write_config8(dev, 0x50, c); + outb(2, 0x80); // now go ahead and set up com1. // set address vt8231_writesuper(0xf4, 0xfe); |