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authorRudolf Marek <r.marek@assembler.cz>2007-11-13 15:40:21 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2007-11-13 15:40:21 +0000
commitcc3ccdb6434402098c1648af12d932c15d3b35e7 (patch)
treeca51d03442b3d325c2529d7b96b06dc088242003 /src/southbridge/via
parent3adc30eed5b0e3c380893560d96bb754796d960c (diff)
downloadcoreboot-cc3ccdb6434402098c1648af12d932c15d3b35e7.tar.xz
Add support for FID/VID changes messages.
Upon incoming SMAF message from CPU (C3 or FID/VID change), the SB will assert SLP# which is connected to LDTSTOP_L on K8 CPUs. Question is for how long. Imho for 100us. Which is more than plenty (2us required) I will try to justify this once I know what bios to set in SB. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via')
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_lpc.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c
index 4af73af263..5d2579e530 100644
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c
@@ -222,6 +222,13 @@ void setup_pm(device_t dev)
/* SCI is generated for RTC/pwrBtn/slpBtn. */
outw(0x001, VT8237R_ACPI_IO_BASE + 0x04);
+
+ /* FIXME: Intel needs more bit set for C2/C3. */
+
+ /* Allow SLP# signal to assert LDTSTOP_L.
+ * Will work for C3 and for FID/VID change.
+ */
+ outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
}
static void vt8237r_init(struct device *dev)