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authorStefan Reinauer <stepan@coresystems.de>2010-02-08 12:20:50 +0000
committerStefan Reinauer <stepan@openbios.org>2010-02-08 12:20:50 +0000
commit38f147ed3d9fdd6bfb23d7226f6fdd3fc5db53d0 (patch)
treeecb680abac7c73798a4abf5f5733c6ad3e179bb4 /src/southbridge/via
parentd51eddbb6611965165ad72eb3fb04377a51ab64a (diff)
downloadcoreboot-38f147ed3d9fdd6bfb23d7226f6fdd3fc5db53d0.tar.xz
janitor task: unify and cleanup naming.
cache_as_ram_auto.c and auto.c are both called "romstage.c" now. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via')
-rw-r--r--src/southbridge/via/vt8231/vt8231_ide.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/via/vt8231/vt8231_ide.c b/src/southbridge/via/vt8231/vt8231_ide.c
index c17ab2edd9..a151ca06c9 100644
--- a/src/southbridge/via/vt8231/vt8231_ide.c
+++ b/src/southbridge/via/vt8231/vt8231_ide.c
@@ -13,7 +13,7 @@ static void ide_init(struct device *dev)
if (!conf->enable_native_ide) {
// Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
// interrupts. Using PCI ints confuses linux for some reason.
- /* Setting reg 0x42 here does not work. It is set in mainboard/auto.c
+ /* Setting reg 0x42 here does not work. It is set in mainboard/romstage.c
* It probably can only be changed while the IDE is disabled
* or it is possibly a timing issue. Ben Hewson 29 Apr 2007.
*/