diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-24 02:38:24 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-31 03:47:24 +0000 |
| commit | cea7e8bdefbc359f9ad04ea3dfe8f3e1d3e13369 (patch) | |
| tree | 04ddbfb655c1f1cd426b171d18812dd8998dd5f3 /src/southbridge/via | |
| parent | ef3f94a5db9228cc668a61bdd3065cd41da2fc55 (diff) | |
| download | coreboot-cea7e8bdefbc359f9ad04ea3dfe8f3e1d3e13369.tar.xz | |
Remove VIA vt8237r southbridge support
Change-Id: I2d0400212d32c4dee71163d2f5919c290b8c0616
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/via')
22 files changed, 0 insertions, 3282 deletions
diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig deleted file mode 100644 index 8f153a8d99..0000000000 --- a/src/southbridge/via/vt8237r/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008-2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOUTHBRIDGE_VIA_VT8237R - bool - select HAVE_DEBUG_SMBUS - select IOAPIC - -if SOUTHBRIDGE_VIA_VT8237R - -config EPIA_VT8237R_INIT - bool - default n - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/via/vt8237r/bootblock.c" - -endif diff --git a/src/southbridge/via/vt8237r/Makefile.inc b/src/southbridge/via/vt8237r/Makefile.inc deleted file mode 100644 index e8946a5d61..0000000000 --- a/src/southbridge/via/vt8237r/Makefile.inc +++ /dev/null @@ -1,30 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ifeq ($(CONFIG_SOUTHBRIDGE_VIA_VT8237R),y) - -ramstage-y += vt8237r.c -ramstage-y += ctrl.c -ramstage-y += ide.c -ramstage-y += lpc.c -ramstage-y += sata.c -ramstage-y += usb.c -ramstage-$(CONFIG_PIRQ_ROUTE) += pirq.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -romstage-y += early_smbus.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c - -endif diff --git a/src/southbridge/via/vt8237r/acpi/default_irq_route.asl b/src/southbridge/via/vt8237r/acpi/default_irq_route.asl deleted file mode 100644 index 351507861c..0000000000 --- a/src/southbridge/via/vt8237r/acpi/default_irq_route.asl +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk> - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Method (_PRT, 0) { - If (LEqual (^ISAC.APIC, Zero)) { - Return (Package (20) { - /* AGP bridge */ - Package (4) { 0x0001ffff, 0, ^ISAC.LNKA, 0x00 }, - Package (4) { 0x0001ffff, 1, ^ISAC.LNKB, 0x00 }, - Package (4) { 0x0001ffff, 2, ^ISAC.LNKC, 0x00 }, - Package (4) { 0x0001ffff, 3, ^ISAC.LNKD, 0x00 }, - - /* IDE interface */ - Package (4) { 0x000fffff, 0, ^ISAC.LNKA, 0x00 }, - Package (4) { 0x000fffff, 1, ^ISAC.LNKB, 0x00 }, - Package (4) { 0x000fffff, 2, ^ISAC.LNKC, 0x00 }, - Package (4) { 0x000fffff, 3, ^ISAC.LNKD, 0x00 }, - - /* USB controller */ - Package (4) { 0x0010ffff, 0, ^ISAC.LNKA, 0x00 }, - Package (4) { 0x0010ffff, 1, ^ISAC.LNKB, 0x00 }, - Package (4) { 0x0010ffff, 2, ^ISAC.LNKC, 0x00 }, - Package (4) { 0x0010ffff, 3, ^ISAC.LNKD, 0x00 }, - - /* Audio (& LPC bridge) */ - Package (4) { 0x0011ffff, 0, ^ISAC.LNKA, 0x00 }, - Package (4) { 0x0011ffff, 1, ^ISAC.LNKB, 0x00 }, - Package (4) { 0x0011ffff, 2, ^ISAC.LNKC, 0x00 }, - Package (4) { 0x0011ffff, 3, ^ISAC.LNKD, 0x00 }, - - /* Ethernet controller */ - Package (4) { 0x0012ffff, 0, ^ISAC.LNKA, 0x00 }, - Package (4) { 0x0012ffff, 1, ^ISAC.LNKB, 0x00 }, - Package (4) { 0x0012ffff, 2, ^ISAC.LNKC, 0x00 }, - Package (4) { 0x0012ffff, 3, ^ISAC.LNKD, 0x00 } - }) - } Else { - /* "Table 9. APIC Fixed IRQ Routing - * When the internal APIC is enabled, internal IRQ - * routing to the APIC is fixed as follows:" */ - Return (Package (20) { - /* The graphics controller behind the AGP bridge */ - /* INTA# => IRQ16 INTB# => IRQ17 INTC# => IRQ18 INTD# => IRQ19 */ - Package (4) { 0x0001ffff, 0, 0x00, 16 }, - Package (4) { 0x0001ffff, 1, 0x00, 17 }, - Package (4) { 0x0001ffff, 2, 0x00, 18 }, - Package (4) { 0x0001ffff, 3, 0x00, 19 }, - - /* IDE (Native Mode)/SATA IRQ & INTE => IRQ20 */ - Package (4) { 0x000fffff, 0, 0x00, 20 }, - Package (4) { 0x000fffff, 1, 0x00, 20 }, - Package (4) { 0x000fffff, 2, 0x00, 20 }, - Package (4) { 0x000fffff, 3, 0x00, 20 }, - - /* USB IRQ (all 5 functions) and INTF => IRQ21 */ - Package (4) { 0x0010ffff, 0, 0x00, 21 }, - Package (4) { 0x0010ffff, 1, 0x00, 21 }, - Package (4) { 0x0010ffff, 2, 0x00, 21 }, - Package (4) { 0x0010ffff, 3, 0x00, 21 }, - - /* AC'97 / MC'97 IRQ and INTG => IRQ22 */ - Package (4) { 0x0011ffff, 0, 0x00, 22 }, - Package (4) { 0x0011ffff, 1, 0x00, 22 }, - Package (4) { 0x0011ffff, 2, 0x00, 22 }, - Package (4) { 0x0011ffff, 3, 0x00, 22 }, - - /* LAN IRQ and INTH => IRQ23 */ - Package (4) { 0x0012ffff, 0, 0x00, 23 }, - Package (4) { 0x0012ffff, 1, 0x00, 23 }, - Package (4) { 0x0012ffff, 2, 0x00, 23 }, - Package (4) { 0x0012ffff, 3, 0x00, 23 } - }) - - } -} diff --git a/src/southbridge/via/vt8237r/acpi/irqlinks.asl b/src/southbridge/via/vt8237r/acpi/irqlinks.asl deleted file mode 100644 index 6c4c89a77f..0000000000 --- a/src/southbridge/via/vt8237r/acpi/irqlinks.asl +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk> - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/x86/acpi/statdef.asl> - -/* Possible PNP IRQs */ -Name (PIRQ, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {3, 4, 6, 7, 10, 11, 12} -}) - -#define IRQ_LINK(reg) \ - Name (_HID, EisaId ("PNP0C0F")) \ - Name (_UID, 1) \ - \ - Method (_STA, 0) { \ - If (LEqual (reg, 0x00)) { \ - Return (STA_DISABLED) \ - } \ - Return (STA_INVISIBLE) \ - } \ - \ - Method (_PRS, 0) { \ - Return (PIRQ) \ - } \ - \ - Name (CRSA, ResourceTemplate () { \ - IRQ (Level, ActiveLow, Shared) {} \ - }) \ - Method (_CRS, 0) { \ - CreateWordField (CRSA, 0x1, AINT) \ - ShiftLeft (One, reg, AINT) \ - Return (CRSA) \ - } \ - \ - Method (_SRS, 1) { \ - CreateWordField (Arg0, 0x1, AINT) \ - Store (Zero, Local0) \ - Store (AINT, Local1) \ - While (LNotEqual (Local1, One)) { \ - ShiftRight (Local1, One, Local1) \ - Increment (Local0) \ - } \ - Store (Local0, reg) \ - } \ - \ - Method (_DIS, 0) { \ - Store (Zero, reg) \ - } \ - -Device (LNKA) { IRQ_LINK (INTA) } -Device (LNKB) { IRQ_LINK (INTB) } -Device (LNKC) { IRQ_LINK (INTC) } -Device (LNKD) { IRQ_LINK (INTD) } diff --git a/src/southbridge/via/vt8237r/acpi/lpc.asl b/src/southbridge/via/vt8237r/acpi/lpc.asl deleted file mode 100644 index f13a96bb29..0000000000 --- a/src/southbridge/via/vt8237r/acpi/lpc.asl +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk> - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* VT8237 ISA bridge */ -Device (ISAC) -{ - Name (_ADR, 0x00110000) - - OperationRegion (ISAB, PCI_Config, 0x00, 0xEF) - Field (ISAB, DWordAcc, NoLock, Preserve) { - - /* PCI PNP Interrupt Routing 1 */ - Offset (0x55), - , 4, /* Reserved */ - INTA, 4, /* PCI INTA# Routing */ - - /* PCI PNP Interrupt Routing 2 */ - Offset (0x56), - INTB, 4, /* PCI INTB# Routing */ - INTC, 4, /* PCI INTC# Routing */ - - /* PCI PNP Interrupt Routing 3 */ - Offset (0x57), - , 4, /* Reserved */ - INTD, 4, /* PCI INTD# Routing */ - - /* Miscellaneous Control 0 */ - Offset (0x58), - , 6, - APIC, 1, /* Internal APIC Enable */ - } - - #include "irqlinks.asl" -} diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c deleted file mode 100644 index 261acde0ce..0000000000 --- a/src/southbridge/via/vt8237r/bootblock.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci_ids.h> - -static void bootblock_southbridge_init(void) -{ - pci_devfn_t dev; - /* don't walk other busses, HT is not enabled */ - - /* ROM decode last 8MB FF800000 - FFFFFFFF on VT8237S/VT8237A */ - /* ROM decode last 4MB FFC00000 - FFFFFFFF on VT8237R */ - - /* Power management controller */ - dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); - - if (dev != PCI_DEV_INVALID) - goto found; - - /* Power management controller */ - dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); - - if (dev != PCI_DEV_INVALID) - goto found; - - /* Power management controller */ - dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); - - if (dev == PCI_DEV_INVALID) - return; - -found: - pci_write_config8(dev, 0x41, 0x7f); -} diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h deleted file mode 100644 index 0ce912e583..0000000000 --- a/src/southbridge/via/vt8237r/chip.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_VIA_VT8237R_CHIP_H -#define SOUTHBRIDGE_VIA_VT8237R_CHIP_H - -#include <stdint.h> - -struct southbridge_via_vt8237r_config { - /** - * Function disable. 1 = disabled. - * 7 Dev 17 fn 6 MC97 - * 6 Dev 17 fn 5 AC97 - * 5 Dev 16 fn 1 USB 1.1 UHCI Ports 2-3 - * 4 Dev 16 fn 0 USB 1.1 UHCI Ports 0-1 - * 3 Dev 15 fn 0 Serial ATA - * 2 Dev 16 fn 2 USB 1.1 UHCI Ports 4-5 - * 1 Dev 16 fn 4 USB 2.0 EHCI - * 0 Dev 16 fn 3 USB 1.1 UHCI Ports 6-7 - */ - u16 fn_ctrl_lo; - - /** - * 7 USB Device Mode 1=dis - * 6 Reserved - * 5 Internal LAN Controller Clock Gating 1=gated - * 4 Internal LAN Controller 1=dis - * 3 Internal RTC 1=en - * 2 Internal PS2 Mouse 1=en - * 1 Internal KBC Configuration 0=dis ports 0x2e/0x2f off 0xe0-0xef - * 0 Internal Keyboard Controller 1=en - */ - u16 fn_ctrl_hi; - - u8 ide0_enable; - u8 ide1_enable; - - /* 1 = 80-pin cable, 0 = 40-pin cable */ - u8 ide0_80pin_cable; - u8 ide1_80pin_cable; - - u8 usb2_termination_set; - u8 usb2_termination_a; - u8 usb2_termination_b; - u8 usb2_termination_c; - u8 usb2_termination_d; - u8 usb2_termination_e; - u8 usb2_termination_f; - u8 usb2_termination_g; - u8 usb2_termination_h; - - u8 usb2_dpll_set; - u8 usb2_dpll_delay; - - u8 int_efgh_as_gpio; - u8 enable_gpo3; - u8 disable_gpo26_gpo27; - u8 enable_aol_2_smb_slave; - u8 enable_gpo5; - u8 gpio15_12_dir_output; -}; - -#endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/ctrl.c b/src/southbridge/via/vt8237r/ctrl.c deleted file mode 100644 index 27761e6444..0000000000 --- a/src/southbridge/via/vt8237r/ctrl.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz> - * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <device/pci_ids.h> -#include <console/console.h> -#include "vt8237r.h" - -/* We support here K8M890/K8T890 and VT8237/S/A PCI1/Vlink */ - -static void vt8237_cfg(struct device *dev) -{ - u8 regm; - struct device *devfun3; - - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T800_DRAM, 0); - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_3, 0); - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_3, 0); - if (!devfun3) - die("Unknown NB"); - - /* CPU to PCI Flow Control 1 & 2, just fill in recommended. */ - pci_write_config8(dev, 0x70, 0xc2); - pci_write_config8(dev, 0x71, 0xc8); - - /* PCI Control */ - pci_write_config8(dev, 0x72, 0xee); - pci_write_config8(dev, 0x73, 0x01); - pci_write_config8(dev, 0x74, 0x3c); - pci_write_config8(dev, 0x75, 0x0f); - pci_write_config8(dev, 0x76, 0x50); - pci_write_config8(dev, 0x77, 0x48); - pci_write_config8(dev, 0x78, 0x01); - /* APIC on HT */ - /* Maybe Enable LDT APIC Mode bit3 set to 1 */ - pci_write_config8(dev, 0x7c, 0x77); - - /* WARNING: Need to copy some registers from NB (D0F3) to SB (D11F7). */ - - regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ - pci_write_config8(dev, 0x57, regm); - - regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ - pci_write_config8(dev, 0x61, regm); - - regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ - pci_write_config8(dev, 0x62, regm); - - /* Shadow page F + memhole copy */ - regm = pci_read_config8(devfun3, 0x83); - pci_write_config8(dev, 0x63, regm); - - regm = pci_read_config8(devfun3, 0x82);/* Shadow page E */ - pci_write_config8(dev, 0x64, regm); - - regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ - pci_write_config8(dev, 0xe6, regm); -} - -/** - * Example of setup: Setup the V-Link for VT8237R, 8X mode. - * - * For K8T890CF VIA recommends what is in VIA column, AW is award 8X: - * - * REG DEF AW VIA-8X VIA-4X - * ----------------------------- - * NB V-Link Manual Driving Control strobe 0xb5 0x46 0x46 0x88 0x88 - * NB V-Link Manual Driving Control - Data 0xb6 0x46 0x46 0x88 0x88 - * NB V-Link Receiving Strobe Delay 0xb7 0x02 0x02 0x61 0x01 - * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4 0x10 0x10 0x11 0x11 - * SB V-Link Strobe Drive Control 0xb9 0x00 0xa5 0x98 0x98 - * SB V-Link Data drive Control???? 0xba 0x00 0xbb 0x77 0x77 - * SB V-Link Receive Strobe Delay???? 0xbb 0x04 0x11 0x11 0x11 - * SB V-Link Compensation Control bit0 (use b9) 0xb8 0x00 0x01 0x01 0x01 - * V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03 - * V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03 - */ - -/* we setup 533MB/s mode full duplex */ - -static void vt8237s_vlink_init(struct device *dev) -{ - u8 reg; - struct device *devfun7; - - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_7, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_7, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_7, 0); - /* No pairing NB was found. */ - if (!devfun7) - { - printk(BIOS_DEBUG, "vt8237s_vlink_init: No pairing NB was found.\n"); - return; - } - - /* - * This init code is valid only for the VT8237S! For different - * southbridges (e.g. VT8237A, VT8237S, VT8237R (without plus R) - * and VT8251) a different init code is required. - */ - - /* disable auto disconnect */ - reg = pci_read_config8(devfun7, 0x42); - reg &= ~0x4; - pci_write_config8(devfun7, 0x42, reg); - - /* NB part setup */ - pci_write_config8(devfun7, 0xb5, 0x66); - pci_write_config8(devfun7, 0xb6, 0x66); - pci_write_config8(devfun7, 0xb7, 0x64); - - reg = pci_read_config8(devfun7, 0xb4); - reg |= 0x1; - reg &= ~0x10; - pci_write_config8(devfun7, 0xb4, reg); - - pci_write_config8(devfun7, 0xb0, 0x6); - pci_write_config8(devfun7, 0xb1, 0x1); - - /* SB part setup */ - pci_write_config8(dev, 0xb7, 0x60); - pci_write_config8(dev, 0xb9, 0x88); - pci_write_config8(dev, 0xba, 0x88); - pci_write_config8(dev, 0xbb, 0x89); - - reg = pci_read_config8(dev, 0xbd); - reg |= 0x3; - reg &= ~0x4; - pci_write_config8(dev, 0xbd, reg); - - reg = pci_read_config8(dev, 0xbc); - reg &= ~0x7; - pci_write_config8(dev, 0xbc, reg); - - /* Program V-link 8X 8bit full duplex, parity enabled. */ - pci_write_config8(dev, 0x48, 0x23 | 0x80); - - /* enable auto disconnect, for STPGNT and HALT */ - reg = pci_read_config8(devfun7, 0x42); - reg |= 0x7; - pci_write_config8(devfun7, 0x42, reg); - -} - -static void vt8237a_vlink_init(struct device *dev) -{ - u8 reg; - struct device *devfun7; - - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_7, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_7, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_7, 0); - /* No pairing NB was found. */ - if (!devfun7) - { - printk(BIOS_DEBUG, "vt8237a_vlink_init: No pairing NB was found.\n"); - return; - } - - /* - * This init code is valid only for the VT8237A! For different - * southbridges (e.g. VT8237S, VT8237R and VT8251) a different - * init code is required. - * - * FIXME: This is based on vt8237r_vlink_init() in - * k8t890/k8t890_ctrl.c and modified to fit what the AMI - * BIOS on my M2V wrote to these registers (by looking - * at lspci -nxxx output). - * Works for me. - */ - - /* disable auto disconnect */ - reg = pci_read_config8(devfun7, 0x42); - reg &= ~0x4; - pci_write_config8(devfun7, 0x42, reg); - - /* NB part setup */ - pci_write_config8(devfun7, 0xb5, 0x88); - pci_write_config8(devfun7, 0xb6, 0x88); - pci_write_config8(devfun7, 0xb7, 0x61); - - reg = pci_read_config8(devfun7, 0xb4); - reg |= 0x11; - pci_write_config8(devfun7, 0xb4, reg); - - pci_write_config8(devfun7, 0xb0, 0x6); - pci_write_config8(devfun7, 0xb1, 0x1); - - /* SB part setup */ - pci_write_config8(dev, 0xb7, 0x50); - pci_write_config8(dev, 0xb9, 0x88); - pci_write_config8(dev, 0xba, 0x8a); - pci_write_config8(dev, 0xbb, 0x88); - - reg = pci_read_config8(dev, 0xbd); - reg |= 0x3; - reg &= ~0x4; - pci_write_config8(dev, 0xbd, reg); - - reg = pci_read_config8(dev, 0xbc); - reg &= ~0x7; - pci_write_config8(dev, 0xbc, reg); - - pci_write_config8(dev, 0x48, 0x23); - - /* enable auto disconnect, for STPGNT and HALT */ - reg = pci_read_config8(devfun7, 0x42); - reg |= 0x7; - pci_write_config8(devfun7, 0x42, reg); -} - -static void ctrl_enable(struct device *dev) -{ - /* Enable the 0:13 and 0:13.1. */ - /* FIXME */ - pci_write_config8(dev, 0x4f, 0x43); -} - -static void ctrl_init(struct device *dev) -{ - /* - * TODO: Fix some ordering issue for V-link set Rx77[6] and - * PCI1_Rx4F[0] should to 1. - * FIXME DO you need? - */ - - /* - * VT8237R specific configuration. Other SB are done in their own - * directories. TODO: Add A version. - */ - struct device *devsb = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC, - 0); - if (devsb) { - vt8237s_vlink_init(dev); - } - - devsb = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); - if (devsb) { - vt8237a_vlink_init(dev); - } - - /* Configure PCI1 and copy mirror registers from D0F3. */ - vt8237_cfg(dev); - dump_south(dev); -} - -static const struct device_operations ctrl_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ctrl_init, - .enable = ctrl_enable, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver_t __pci_driver = { - .ops = &ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237_VLINK, -}; diff --git a/src/southbridge/via/vt8237r/early_serial.c b/src/southbridge/via/vt8237r/early_serial.c deleted file mode 100644 index 9249da6f7e..0000000000 --- a/src/southbridge/via/vt8237r/early_serial.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Enable the serial devices on the VIA - */ - - -/* The base address is 0x15c, 0x2e, depending on config bytes */ - -#define SIO_BASE 0x3f0 -#define SIO_DATA SIO_BASE+1 - -static void vt8237r_writepnpaddr(uint8_t val) -{ - outb(val, 0x2e); - outb(val, 0xeb); -} - -static void vt8237r_writepnpdata(uint8_t val) -{ - outb(val, 0x2f); - outb(val, 0xeb); -} - - -static void vt8237r_writesiobyte(uint16_t reg, uint8_t val) -{ - outb(val, reg); -} - -static void vt8237r_writesioword(uint16_t reg, uint16_t val) -{ - outw(val, reg); -} - - -/* regs we use: 85, and the southbridge devfn is defined by the - mainboard - */ - -static void enable_vt8237r_serial(void) -{ - // turn on pnp - vt8237r_writepnpaddr(0x87); - vt8237r_writepnpaddr(0x87); - // now go ahead and set up com1. - // set address - vt8237r_writepnpaddr(0x7); - vt8237r_writepnpdata(0x2); - // enable serial out - vt8237r_writepnpaddr(0x30); - vt8237r_writepnpdata(0x1); - // serial port 1 base address (FEh) - vt8237r_writepnpaddr(0x60); - vt8237r_writepnpdata(0xfe); - // serial port 1 IRQ (04h) - vt8237r_writepnpaddr(0x70); - vt8237r_writepnpdata(0x4); - // serial port 1 control - vt8237r_writepnpaddr(0xf0); - vt8237r_writepnpdata(0x2); - // turn of pnp - vt8237r_writepnpaddr(0xaa); - - // set up reg to set baud rate. - vt8237r_writesiobyte(0x3fb, 0x80); - // Set 115 kb - vt8237r_writesioword(0x3f8, 1); - // Set 9.6 kb - // WRITESIOWORD(0x3f8, 12) - // now set no parity, one stop, 8 bits - vt8237r_writesiobyte(0x3fb, 3); - // now turn on RTS, DRT - vt8237r_writesiobyte(0x3fc, 3); - // Enable interrupts - vt8237r_writesiobyte(0x3f9, 0xf); - // should be done. Dump a char for fun. - vt8237r_writesiobyte(0x3f8, 48); -} diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c deleted file mode 100644 index 3257cc241d..0000000000 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ /dev/null @@ -1,509 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> - * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#if !defined(__ROMCC__) -#include <arch/acpi.h> -#endif -#include <console/console.h> -#include <arch/io.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <spd.h> -#include <stdlib.h> -#include "vt8237r.h" - -/** - * Print an error, should it occur. If no error, just exit. - * - * @param host_status The data returned on the host status register after - * a transaction is processed. - * @param loops The number of times a transaction was attempted. - */ -static void smbus_print_error(u8 host_status, int loops) -{ - /* Check if there actually was an error. */ - if ((host_status == 0x00 || host_status == 0x40 || - host_status == 0x42) && (loops < SMBUS_TIMEOUT)) - return; - - if (loops >= SMBUS_TIMEOUT) - printk(BIOS_ERR, "SMBus timeout\n"); - if (host_status & (1 << 4)) - printk(BIOS_ERR, "Interrupt/SMI# was Failed Bus Transaction\n"); - if (host_status & (1 << 3)) - printk(BIOS_ERR, "Bus error\n"); - if (host_status & (1 << 2)) - printk(BIOS_ERR, "Device error\n"); - if (host_status & (1 << 1)) - printk(BIOS_DEBUG, "Interrupt/SMI# completed successfully\n"); - if (host_status & (1 << 0)) - printk(BIOS_ERR, "Host busy\n"); -} - -/** - * Wait for the SMBus to become ready to process the next transaction. - */ -static void smbus_wait_until_ready(void) -{ - int loops; - - PRINT_DEBUG("Waiting until SMBus ready\n"); - - /* Loop up to SMBUS_TIMEOUT times, waiting for bit 0 of the - * SMBus Host Status register to go to 0, indicating the operation - * was completed successfully. I don't remember why I did it this way, - * but I think it was because ROMCC was running low on registers */ - loops = 0; - while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT) - ++loops; - - smbus_print_error(inb(SMBHSTSTAT), loops); -} - -/** - * Reset and take ownership of the SMBus. - */ -static void smbus_reset(void) -{ - outb(HOST_RESET, SMBHSTSTAT); - - /* Datasheet says we have to read it to take ownership of SMBus. */ - inb(SMBHSTSTAT); - - PRINT_DEBUG("After reset status: "); - PRINT_DEBUG_HEX16(inb(SMBHSTSTAT)); - PRINT_DEBUG("\n"); -} - -static u8 smbus_transaction(u8 dimm, u8 offset, u8 data, int do_read) -{ - u8 val; - - PRINT_DEBUG(do_read ? "RD: " : "WR: "); - PRINT_DEBUG("ADDR "); - PRINT_DEBUG_HEX16(dimm); - PRINT_DEBUG(" OFFSET "); - PRINT_DEBUG_HEX16(offset); - PRINT_DEBUG("\n"); - - smbus_reset(); - - /* Clear host data port. */ - outb(do_read ? 0x00 : data, SMBHSTDAT0); - SMBUS_DELAY(); - smbus_wait_until_ready(); - - /* Actual addr to reg format. */ - dimm = (dimm << 1); - dimm |= !!do_read; - outb(dimm, SMBXMITADD); - outb(offset, SMBHSTCMD); - - /* Start transaction, byte data read. */ - outb(0x48, SMBHSTCTL); - SMBUS_DELAY(); - smbus_wait_until_ready(); - - val = inb(SMBHSTDAT0); - PRINT_DEBUG("Read: "); - PRINT_DEBUG_HEX16(val); - PRINT_DEBUG("\n"); - - /* Probably don't have to do this, but it can't hurt. */ - smbus_reset(); - - return val; -} - -/** - * Read a byte from the SMBus. - * - * @param dimm The address location of the DIMM on the SMBus. - * @param offset The offset the data is located at. - */ -u8 smbus_read_byte(u8 dimm, u8 offset) -{ - return smbus_transaction(dimm, offset, 0, 1); -} - -void smbus_write_byte(u8 dimm, u8 offset, u8 data) -{ - smbus_transaction(dimm, offset, data, 0); -} - -#define PSONREADY_TIMEOUT 0x7fffffff - -static pci_devfn_t get_vt8237_lpc(void) -{ - pci_devfn_t dev; - - /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); - if (dev != PCI_DEV_INVALID) - return dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); - if (dev != PCI_DEV_INVALID) - return dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); - return dev; -} - -/** - * Enable the SMBus on VT8237R-based systems. - */ -void enable_smbus(void) -{ - pci_devfn_t dev; - int loops; - - /* Power management controller */ - dev = get_vt8237_lpc(); - if (dev == PCI_DEV_INVALID) - die("Power management controller not found\n"); - - /* Make sure the RTC power well is up before touching smbus. */ - loops = 0; - while (!(pci_read_config8(dev, VT8237R_PSON) & (1<<6)) - && loops < PSONREADY_TIMEOUT) - ++loops; - - /* - * 7 = SMBus Clock from RTC 32.768KHz - * 5 = Internal PLL reset from susp - */ - pci_write_config8(dev, VT8237R_POWER_WELL, 0xa0); - - /* Enable SMBus. */ - pci_write_config16(dev, VT8237R_SMBUS_IO_BASE_REG, - VT8237R_SMBUS_IO_BASE | 0x1); - - /* SMBus Host Configuration, enable. */ - pci_write_config8(dev, VT8237R_SMBUS_HOST_CONF, 0x01); - - /* Make it work for I/O. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - smbus_reset(); - - /* Reset the internal pointer. */ - inb(SMBHSTCTL); -} - -/** - * A fixup for some systems that need time for the SMBus to "warm up". This is - * needed on some VT823x based systems, where the SMBus spurts out bad data for - * a short time after power on. This has been seen on the VIA Epia series and - * Jetway J7F2-series. It reads the ID byte from SMBus, looking for - * known-good data from a slot/address. Exits on either good data or a timeout. - * - * TODO: This should probably go into some global file, but one would need to - * be created just for it. If some other chip needs/wants it, we can - * worry about it then. - * - * @param ctrl The memory controller and SMBus addresses. - */ -void smbus_fixup(const u8 channel0[], int ram_slots) -{ - int i, current_slot = 0; - u8 result = 0; - - if (!ram_slots) { - printk(BIOS_ERR, "smbus_fixup() thinks there are no RAM slots!\n"); - return; - } - - PRINT_DEBUG("Waiting for SMBus to warm up"); - - /* - * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for - * the ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between). - * VT8237R has only been seen on DDR and DDR2 based systems, so far. - */ - for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || - (result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++) { - - if (current_slot > ram_slots) - current_slot = 0; - - result = smbus_read_byte(channel0[current_slot], - SPD_MEMORY_TYPE); - current_slot++; - PRINT_DEBUG("."); - } - - if (i >= SMBUS_TIMEOUT) - printk(BIOS_ERR, "SMBus timed out while warming up\n"); - else - PRINT_DEBUG("Done\n"); -} - -/* FIXME: Better separate the NB and SB, will be done once it works. */ - -void vt8237_sb_enable_fid_vid(void) -{ - pci_devfn_t dev, devctl; - u16 devid; - - /* Power management controller */ - dev = get_vt8237_lpc(); - if (dev == PCI_DEV_INVALID) - return; - - devid = pci_read_config16(dev, PCI_DEVICE_ID); - - /* generic setup */ - - /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); - - /* Enable ACPI access RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); - - /* chipset-specific parts */ - - /* VLINK: FIXME: can we drop the device check and just look for the VLINK device? */ - if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC || - devid == PCI_DEVICE_ID_VIA_VT8237A_LPC) { - devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237_VLINK), 0); - - if (devctl != PCI_DEV_INVALID) { - /* So the chip knows we are on AMD. */ - pci_write_config8(devctl, 0x7c, 0x7f); - } - } - - if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) { - /* - * Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. - */ - - outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); - - /* Reduce further the STPCLK/LDTSTP signal to 5us. */ - pci_write_config8(dev, 0xec, 0x4); - - return; - } - - /* VT8237R and VT8237A */ - - /* - * Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. - */ - outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); -} - -void enable_rom_decode(void) -{ - pci_devfn_t dev; - - /* Power management controller */ - dev = get_vt8237_lpc(); - if (dev == PCI_DEV_INVALID) - return; - - /* ROM decode last 1MB FFC00000 - FFFFFFFF. */ - pci_write_config8(dev, 0x41, 0x7f); -} - -int acpi_get_sleep_type(void) -{ - pci_devfn_t dev; - u16 tmp; - - printk(BIOS_DEBUG, "IN TEST WAKEUP\n"); - - /* Power management controller */ - dev = get_vt8237_lpc(); - if (dev == PCI_DEV_INVALID) - die("Power management controller not found\n"); - - /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); - - /* Enable ACPI access RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); - - tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); - - printk(BIOS_DEBUG, "%02x", tmp); - return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; -} - -#if defined(__GNUC__) -void vt8237_early_spi_init(void) -{ - pci_devfn_t dev; - volatile u16 *spireg; - u32 tmp; - - /* Bus Control and Power Management */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); - - if (dev == PCI_DEV_INVALID) - die("SB not found\n"); - - /* Put SPI base 20 d0 fe. */ - tmp = pci_read_config32(dev, 0xbc); - pci_write_config32(dev, 0xbc, - (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000)); - - /* Set SPI clock to 33MHz. */ - spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c); - (*spireg) &= 0xff00; -} -#endif - -/* This #if is special. ROMCC chokes on the (rom == NULL) comparison. - * Since the whole function is only called for one target and that target - * is compiled with GCC, hide the function from ROMCC and be happy. - */ -#if defined(__GNUC__) -/* - * Offset 0x58: - * 31:20 reserved - * 19:16 4 bit position in shadow EEPROM - * 15:0 data to write - * - * Offset 0x5c: - * 31:28 reserved - * 27 ERDBG - enable read from 0x5c - * 26 reserved - * 25 SEELD - * 24 SEEPR - write 1 when done updating, wait until SEELD is - * set to 1, sticky - * cleared by reset, if it is 1 writing is disabled - * 19:16 4 bit position in shadow EEPROM - * 15:0 data from shadow EEPROM - * - * After PCIRESET SEELD and SEEPR must be 1 and 1. - */ - -/* 1 = needs PCI reset, 0 don't reset, network initialized. */ - -/* FIXME: Maybe close the debug register after use? */ - -#define LAN_TIMEOUT 0x7FFFFFFF - -int vt8237_early_network_init(struct vt8237_network_rom *rom) -{ - struct vt8237_network_rom n; - int i, loops; - pci_devfn_t dev; - u32 tmp; - u8 status; - u16 *rom_write; - unsigned int checksum; - - /* Network adapter */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_8233_7), 0); - if (dev == PCI_DEV_INVALID) { - printk(BIOS_ERR, "Network is disabled, please enable\n"); - return 0; - } - - tmp = pci_read_config32(dev, 0x5c); - tmp |= 0x08000000; /* Enable ERDBG. */ - pci_write_config32(dev, 0x5c, tmp); - - status = ((pci_read_config32(dev, 0x5c) >> 24) & 0x3); - - /* Network controller OK, EEPROM loaded. */ - if (status == 3) - return 0; - - if (rom == NULL) { - printk(BIOS_ERR, "No config data specified, using default MAC!\n"); - n.mac_address[0] = 0x0; - n.mac_address[1] = 0x0; - n.mac_address[2] = 0xde; - n.mac_address[3] = 0xad; - n.mac_address[4] = 0xbe; - n.mac_address[5] = 0xef; - n.phy_addr = 0x1; - n.res1 = 0x0; - n.sub_sid = 0x102; - n.sub_vid = 0x1106; - n.pid = 0x3065; - n.vid = 0x1106; - n.pmcc = 0x1f; - n.data_sel = 0x10; - n.pmu_data_reg = 0x0; - n.aux_curr = 0x0; - n.reserved = 0x0; - n.min_gnt = 0x3; - n.max_lat = 0x8; - n.bcr0 = 0x9; - n.bcr1 = 0xe; - n.cfg_a = 0x3; - n.cfg_b = 0x0; - n.cfg_c = 0x40; - n.cfg_d = 0x82; - n.checksum = 0x0; - rom = &n; - } - - rom_write = (u16 *) rom; - checksum = 0; - /* Write all data except checksum and second to last byte. */ - tmp &= 0xff000000; /* Leave reserved bits in. */ - for (i = 0; i < 15; i++) { - pci_write_config32(dev, 0x58, tmp | (i << 16) | rom_write[i]); - /* Lame code FIXME */ - checksum += rom_write[i] & 0xff; - /* checksum %= 256; */ - checksum += (rom_write[i] >> 8) & 0xff; - /* checksum %= 256; */ - } - - checksum += (rom_write[15] & 0xff); - checksum = ~(checksum & 0xff); - tmp |= (((checksum & 0xff) << 8) | rom_write[15]); - - /* Write last byte and checksum. */ - pci_write_config32(dev, 0x58, (15 << 16) | tmp); - - tmp = pci_read_config32(dev, 0x5c); - pci_write_config32(dev, 0x5c, tmp | 0x01000000); /* Toggle SEEPR. */ - - /* Yes, this is a mess, but it's the easiest way to do it. */ - /* XXX not so messy, but an explanation of the hack would have been better */ - loops = 0; - while ((((pci_read_config32(dev, 0x5c) >> 25) & 1) == 0) - && (loops < LAN_TIMEOUT)) { - ++loops; - } - - if (loops >= LAN_TIMEOUT) { - printk(BIOS_ERR, "Timeout - LAN controller didn't accept config\n"); - return 0; - } - - /* We are done, config will be used after PCIRST#. */ - return 1; -} -#endif diff --git a/src/southbridge/via/vt8237r/fadt.c b/src/southbridge/via/vt8237r/fadt.c deleted file mode 100644 index c5cd1d6ccb..0000000000 --- a/src/southbridge/via/vt8237r/fadt.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com> - * Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <arch/acpi.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "vt8237r.h" - -/** - * Create the Fixed ACPI Description Tables (FADT) for any board with this SB. - */ -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - struct device *dev; - int is_vt8237s = 0; - - /* Power management controller */ - dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); - - if (dev) - is_vt8237s = 1; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = 244; - header->revision = 4; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 42; - - fadt->firmware_ctrl = (u32)facs; - fadt->dsdt = (u32)dsdt; - fadt->preferred_pm_profile = 0; - fadt->sci_int = 9; - fadt->smi_cmd = 0; - fadt->acpi_enable = 0; - fadt->acpi_disable = 0; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x0; - - fadt->pm1a_evt_blk = VT8237R_ACPI_IO_BASE; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = VT8237R_ACPI_IO_BASE + 0x4; - fadt->pm1b_cnt_blk = 0x0; - /* once we support C2/C3 this could be set to 0x22 and chipset needs to be adjusted too */ - fadt->pm2_cnt_blk = 0x0; - fadt->pm_tmr_blk = VT8237R_ACPI_IO_BASE + 0x8; - fadt->gpe0_blk = VT8237R_ACPI_IO_BASE + 0x20; - if (is_vt8237s) { - fadt->gpe1_blk = VT8237R_ACPI_IO_BASE + 0x60; - fadt->gpe1_base = 0x10; - fadt->gpe1_blk_len = 4; - } else { - fadt->gpe1_blk = 0x0; - fadt->gpe1_base = 0; - fadt->gpe1_blk_len = 0; - } - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 0; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 4; - - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 90; - fadt->p_lvl3_lat = 900; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 0; - fadt->duty_width = 1; //?? - fadt->day_alrm = 0x7d; - fadt->mon_alrm = 0x7e; - fadt->century = 0x32; - /* We have legacy devices, 8042, VGA is ok to probe, MSI are not supported */ - fadt->iapc_boot_arch = 0xb; - /* check me */ - fadt->flags = 0xa5; - - fadt->reset_reg.space_id = 0; - fadt->reset_reg.bit_width = 0; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0x0; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 0; - fadt->x_firmware_ctl_l = (u32)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/southbridge/via/vt8237r/ide.c b/src/southbridge/via/vt8237r/ide.c deleted file mode 100644 index ac9a5e781c..0000000000 --- a/src/southbridge/via/vt8237r/ide.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Based on other VIA SB code. */ - -#include <compiler.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <console/console.h> -#include "vt8237r.h" -#include "chip.h" - -/** - * Cable type detect function, weak so it can be overloaded in mainboard.c - */ -u32 __weak vt8237_ide_80pin_detect(struct device *dev) -{ - struct southbridge_via_vt8237r_config *sb = - (struct southbridge_via_vt8237r_config *)dev->chip_info; - u32 res; - res = sb->ide0_80pin_cable ? VT8237R_IDE0_80PIN_CABLE : 0; - res |= sb->ide1_80pin_cable ? VT8237R_IDE1_80PIN_CABLE : 0; - return res; -} - -/** - * No native mode. Interrupts from unconnected HDDs might occur if - * IRQ14/15 is used for PCI. Therefore no native mode support. - */ -static void ide_init(struct device *dev) -{ - struct southbridge_via_vt8237r_config *sb = - (struct southbridge_via_vt8237r_config *)dev->chip_info; - - u8 enables; - u32 cablesel; - - printk(BIOS_INFO, "%s IDE interface %s\n", "Primary", - sb->ide0_enable ? "enabled" : "disabled"); - printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary", - sb->ide1_enable ? "enabled" : "disabled"); - enables = pci_read_config8(dev, IDE_CS) & ~0x3; - enables |= (sb->ide0_enable << 1) | sb->ide1_enable; - pci_write_config8(dev, IDE_CS, enables); - enables = pci_read_config8(dev, IDE_CS); - printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables); - - /* Enable only compatibility mode. */ - enables = pci_read_config8(dev, 0x09); - enables &= 0xFA; - pci_write_config8(dev, 0x09, enables); - - enables = pci_read_config8(dev, IDE_CONF_II); - enables &= ~0xc0; - pci_write_config8(dev, IDE_CONF_II, enables); - enables = pci_read_config8(dev, IDE_CONF_II); - printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables); - - /* Enable prefetch buffers. */ - enables = pci_read_config8(dev, IDE_CONF_I); - enables |= 0xf0; - pci_write_config8(dev, IDE_CONF_I, enables); - - /* Flush FIFOs at half. */ - enables = pci_read_config8(dev, IDE_CONF_FIFO); - enables &= 0xf0; - enables |= (1 << 2) | (1 << 0); - pci_write_config8(dev, IDE_CONF_FIFO, enables); - - /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */ - enables = pci_read_config8(dev, IDE_MISC_I); - enables &= 0xe2; - enables |= (1 << 4) | (1 << 3); - pci_write_config8(dev, IDE_MISC_I, enables); - - /* Use memory read multiple, Memory-Write-and-Invalidate. */ - enables = pci_read_config8(dev, IDE_MISC_II); - enables &= 0xEF; - enables |= (1 << 2) | (1 << 3); - pci_write_config8(dev, IDE_MISC_II, enables); - - /* Force interrupts to use compat mode. */ - pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); - pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); - - /* Cable guy... */ - cablesel = pci_read_config32(dev, IDE_UDMA); - cablesel &= ~VT8237R_IDE_CABLESEL_MASK; - cablesel |= vt8237_ide_80pin_detect(dev); - pci_write_config32(dev, IDE_UDMA, cablesel); - -#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - struct device *lpc_dev; - - /* Set PATA Output Drive Strength */ - lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); - if (lpc_dev) - pci_write_config8(lpc_dev, 0x7C, 0x20); -#endif -} - -static const struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_82C586_1, -}; diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c deleted file mode 100644 index 998340f419..0000000000 --- a/src/southbridge/via/vt8237r/lpc.c +++ /dev/null @@ -1,686 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz> - * Copyright (C) 2009 Jon Harrison <bothlyn@blueyonder.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Inspiration from other VIA SB code. */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <pc80/mc146818rtc.h> -#include <arch/ioapic.h> -#include <cpu/x86/lapic.h> -#include <cpu/cpu.h> -#include <pc80/keyboard.h> -#include <pc80/i8259.h> -#include <stdlib.h> -#include <arch/acpi.h> -#include "vt8237r.h" -#include "chip.h" - -static void southbridge_init_common(struct device *dev); - -#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - /* Interrupts for INT# A B C D */ -static const unsigned char pciIrqs[4] = { 10, 11, 12, 0}; - - /* Interrupt Assignments for Pins 1 2 3 4 */ -static const unsigned char sataPins[4] = { 'A','B','C','D'}; -static const unsigned char vgaPins[4] = { 'A','B','C','D'}; -static const unsigned char usbPins[4] = { 'A','B','C','D'}; -static const unsigned char enetPins[4] = { 'A','B','C','D'}; -static const unsigned char vt8237Pins[4] = { 'A','B','C','D'}; -static const unsigned char slotPins[4] = { 'C','D','A','B'}; -static const unsigned char riserPins[4] = { 'D','C','B','A'}; - -static unsigned char *pin_to_irq(const unsigned char *pin) -{ - static unsigned char Irqs[4]; - int i; - for (i = 0; i < 4; i++) - Irqs[i] = pciIrqs[ pin[i] - 'A' ]; - - return Irqs; -} -#endif - -/** Set up PCI IRQ routing, route everything through APIC. */ -static void pci_routing_fixup(struct device *dev) -{ -#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - struct device *pdev; -#endif - - /* PCI PNP Interrupt Routing INTE/F - disable */ - pci_write_config8(dev, 0x44, 0x00); - - /* PCI PNP Interrupt Routing INTG/H - disable */ - pci_write_config8(dev, 0x45, 0x00); - - /* Gate Interrupts until RAM Writes are flushed */ - pci_write_config8(dev, 0x49, 0x20); - -#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - - /* Share INTE-INTH with INTA-INTD as per stock BIOS. */ - pci_write_config8(dev, 0x46, 0x00); - - /* setup PCI IRQ routing (For PCI Slot)*/ - pci_write_config8(dev, 0x55, pciIrqs[0] << 4); - pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) ); - pci_write_config8(dev, 0x57, pciIrqs[3] << 4); - - /* PCI Routing Fixup */ - - //Setup MiniPCI Slot - pci_assign_irqs(0, 0x14, pin_to_irq(slotPins)); - - // Via 2 slot riser card 2nd slot - pci_assign_irqs(0, 0x13, pin_to_irq(riserPins)); - - //Setup USB - pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); - - //Setup VT8237R Sound - pci_assign_irqs(0, 0x11, pin_to_irq(vt8237Pins)); - - //Setup Ethernet - pci_assign_irqs(0, 0x12, pin_to_irq(enetPins)); - - //Setup VGA - pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins)); - - /* APIC Routing Fixup */ - - // Setup SATA - pdev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT6420_SATA, 0); - pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x02); - pci_assign_irqs(0, 0x0f, pin_to_irq(sataPins)); - - - // Setup PATA Override - pdev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_82C586_1, 0); - pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x01); - pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); - -#else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); - - /* PCI Interrupt Polarity */ - pci_write_config8(dev, 0x54, 0x00); - - /* PCI INTA# Routing */ - pci_write_config8(dev, 0x55, 0x00); - - /* PCI INTB#/C# Routing */ - pci_write_config8(dev, 0x56, 0x00); - - /* PCI INTD# Routing */ - pci_write_config8(dev, 0x57, 0x00); -#endif -} - - - -/** - * Set up the power management capabilities directly into ACPI mode. - * This avoids having to handle any System Management Interrupts (SMIs). - */ - -static void setup_pm(struct device *dev) -{ - u16 tmp; - struct southbridge_via_vt8237r_config *cfg; - - cfg = dev->chip_info; - - /* Debounce LID and PWRBTN# Inputs for 16ms. */ - pci_write_config8(dev, 0x80, 0x20); - - /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); - - /* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */ - pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ); - -#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - /* Primary interrupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ - pci_write_config16(dev, 0x84, 0x3052); -#else - /* Primary interrupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ - pci_write_config16(dev, 0x84, 0x30b2); - -#endif - /* SMI output level to low, 7.5us throttle clock */ - pci_write_config8(dev, 0x8d, 0x18); - - /* GP Timer Control 1s */ - pci_write_config8(dev, 0x93, 0x88); - - /* - * 7 = SMBus clock from RTC 32.768KHz - * 5 = Internal PLL reset from susp disabled - * 2 = GPO2 is SUSA# - */ - tmp = 0xa0; - if (cfg && cfg->enable_gpo3) - tmp |= 0x10; - pci_write_config8(dev, 0x94, tmp); - - /* - * 7 = stp to sust delay 1msec - * 6 = SUSST# Deasserted Before PWRGD for STD - * 5 = Keyboard/Mouse Swap - * 4 = PWRGOOD reset on VT8237A/S - * 3 = GPO26/GPO27 is GPO - * 2 = Disable Alert on Lan - * 1 = SUSCLK/GPO4 - * 0 = USB Wakeup - */ - -#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - pci_write_config8(dev, 0x95, 0xc2); -#else - tmp = 0xcc; - if (cfg) { - if (cfg->disable_gpo26_gpo27) - tmp &= ~0x08; - if (cfg->enable_aol_2_smb_slave) - tmp &= ~0x04; - } - pci_write_config8(dev, 0x95, tmp); -#endif - - /* Disable GP3 timer. */ - pci_write_config8(dev, 0x98, 0); - - /* Enable ACPI access RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); - - /* Clear status events. */ - outw(0xffff, VT8237R_ACPI_IO_BASE + 0x00); - outw(0xffff, VT8237R_ACPI_IO_BASE + 0x20); - outw(0xffff, VT8237R_ACPI_IO_BASE + 0x28); - outl(0xffffffff, VT8237R_ACPI_IO_BASE + 0x30); - - /* Disable SCI on GPIO. */ - outw(0x0, VT8237R_ACPI_IO_BASE + 0x22); - - /* Disable SMI on GPIO. */ - outw(0x0, VT8237R_ACPI_IO_BASE + 0x24); - - /* Disable all global enable SMIs, except SW SMI */ - outw(0x40, VT8237R_ACPI_IO_BASE + 0x2a); - - /* Primary activity SMI disable. */ - outl(0x0, VT8237R_ACPI_IO_BASE + 0x34); - - /* GP timer reload on none. */ - outl(0x0, VT8237R_ACPI_IO_BASE + 0x38); - - /* Disable extended IO traps. */ - outb(0x0, VT8237R_ACPI_IO_BASE + 0x42); - - /* SCI is generated for RTC/pwrBtn/slpBtn. */ - tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); - - /* All SMI on, both IDE buses ON, PSON rising edge. */ - outw(0x1, VT8237R_ACPI_IO_BASE + 0x2c); - - /* clear sleep */ - tmp &= ~(7 << 10); - tmp |= 1; - outw(tmp, VT8237R_ACPI_IO_BASE + 0x04); -} - -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); - return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; -} - -static void vt8237r_init(struct device *dev) -{ - u8 enables; - struct southbridge_via_vt8237r_config *cfg; - - cfg = dev->chip_info; - -#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); - /* - * TODO: Looks like stock BIOS can do this but causes a hang - * Enable SATA LED, disable special CPU Frequency Change - - * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. - * Setup to match EPIA default - * PCS0# on Pin U1 - */ - enables = pci_read_config8(dev, 0xe5); - enables |= 0x23; - pci_write_config8(dev, 0xe5, enables); - - /* - * Enable Flash Write Access. - * Note EPIA-N Does not use REQ5 or PCISTP#(Hang) - */ - enables = pci_read_config8(dev, 0xe4); - enables |= 0x2B; - pci_write_config8(dev, 0xe4, enables); - - /* Enables Extra RTC Ports */ - enables = pci_read_config8(dev, 0x4E); - enables |= 0x80; - pci_write_config8(dev, 0x4E, enables); - -#else - printk(BIOS_SPEW, "Entering vt8237r_init.\n"); - /* - * Enable SATA LED, disable special CPU Frequency Change - - * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. - */ - pci_write_config8(dev, 0xe5, 0x09); - - enables = 0x4; - if (cfg) { - if (cfg->enable_gpo5) - enables |= 0x01; - if (cfg->gpio15_12_dir_output) - enables |= 0x10; - } - /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, enables); -#endif - - /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ - enables = pci_read_config8(dev, 0x4f); - enables |= 0x08; - pci_write_config8(dev, 0x4f, enables); - -#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - /* - * Set Read Pass Write Control Enable - */ - pci_write_config8(dev, 0x48, 0x0c); -#else - /* - * Set Read Pass Write Control Enable - * (force A2 from APIC FSB to low). - */ - pci_write_config8(dev, 0x48, 0x8c); -#endif - - southbridge_init_common(dev); - -#if !IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - /* FIXME: Intel needs more bit set for C2/C3. */ - - /* - * Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. - */ - outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); -#endif - - printk(BIOS_SPEW, "Leaving %s.\n", __func__); - printk(BIOS_SPEW, "And taking a dump:\n"); - dump_south(dev); -} - -static void vt8237a_init(struct device *dev) -{ - /* - * FIXME: This is based on vt8237s_init() and the values the AMI - * BIOS on my M2V wrote to these registers (by looking - * at lspci -nxxx output). - * Works for me. - */ - u32 tmp; - - /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ - tmp = pci_read_config8(dev, 0x4f); - tmp |= 0x08; - pci_write_config8(dev, 0x4f, tmp); - - /* - * bit2: REQ5 as PCI request input - should be together with INTE-INTH. - * bit5: usb power control lines as gpio - */ - pci_write_config8(dev, 0xe4, 0x24); - /* - * Enable APIC wakeup from INTH - * Enable SATA LED, disable special CPU Frequency Change - - * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. - */ - pci_write_config8(dev, 0xe5, 0x69); - - /* Reduce further the STPCLK/LDTSTP signal to 5us. */ - pci_write_config8(dev, 0xec, 0x4); - - /* Host Bus Power Management Control, maybe not needed */ - pci_write_config8(dev, 0x8c, 0x5); - - /* Enable HPET */ - pci_write_config32(dev, 0x68, (CONFIG_HPET_ADDRESS | 0x80)); - - southbridge_init_common(dev); - - /* Share INTE-INTH with INTA-INTD for simplicity */ - pci_write_config8(dev, 0x46, 0x00); - - /* FIXME: Intel needs more bit set for C2/C3. */ - - /* - * Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. - */ - outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); - - dump_south(dev); -} - -static void vt8237s_init(struct device *dev) -{ - u32 tmp; - - /* Put SPI base VT8237S_SPI_MEM_BASE. */ - tmp = pci_read_config32(dev, 0xbc); - pci_write_config32(dev, 0xbc, - (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000)); - - /* - * REQ5 as PCI request input - should be together with INTE-INTH. - */ - pci_write_config8(dev, 0xe4, 0x04); - - /* Reduce further the STPCLK/LDTSTP signal to 5us. */ - pci_write_config8(dev, 0xec, 0x4); - - /* Host Bus Power Management Control, maybe not needed */ - pci_write_config8(dev, 0x8c, 0x5); - - /* Enable HPET, does not work correctly on R. */ - pci_write_config32(dev, 0x68, (CONFIG_HPET_ADDRESS | 0x80)); - - southbridge_init_common(dev); - - /* FIXME: Intel needs more bit set for C2/C3. */ - - /* - * Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2. - */ - outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); - - dump_south(dev); -} - -static void vt8237_common_init(struct device *dev) -{ - u8 enables, byte; - struct southbridge_via_vt8237r_config *cfg; -#if !IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - unsigned char pwr_on; -#endif - - cfg = dev->chip_info; - - /* Enable addr/data stepping. */ - byte = pci_read_config8(dev, PCI_COMMAND); - byte |= PCI_COMMAND_WAIT; - pci_write_config8(dev, PCI_COMMAND, byte); - -/* EPIA-N(L) Uses CN400 for BIOS Access */ -#if !IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - /* Enable the internal I/O decode. */ - enables = pci_read_config8(dev, 0x6C); - enables |= 0x80; - pci_write_config8(dev, 0x6C, enables); - - /* - * ROM decode - * bit range - * 7 000E0000h-000EFFFFh - * 6 FFF00000h-FFF7FFFFh - * 5 FFE80000h-FFEFFFFFh - * 4 FFE00000h-FFE7FFFFh - * 3 FFD80000h-FFDFFFFFh - * 2 FFD00000h-FFD7FFFFh - * 1 FFC80000h-FFCFFFFFh - * 0 FFC00000h-FFC7FFFFh - * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte. - */ - pci_write_config8(dev, 0x41, 0x7f); -#endif - - /* - * Set bit 6 of 0x40 (I/O recovery time). - * IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so - * that PCI interrupts can be properly marked as level triggered. - */ - enables = pci_read_config8(dev, 0x40); - enables |= 0x44; - pci_write_config8(dev, 0x40, enables); - - /* Line buffer control */ - enables = pci_read_config8(dev, 0x42); - enables |= 0xf8; - pci_write_config8(dev, 0x42, enables); - - /* Delay transaction control */ - pci_write_config8(dev, 0x43, 0xb); - -#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - /* I/O recovery time, default IDE routing */ - pci_write_config8(dev, 0x4c, 0x04); - - /* ROM memory cycles go to LPC. */ - pci_write_config8(dev, 0x59, 0x80); - - /* - * Bit | Meaning - * ------------- - * 3 | Bypass APIC De-Assert Message (1=Enable) - * 2 | APIC HyperTransport Mode (1=Enable) - * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI" - * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch - * 0 | Dynamic Clock Gating Main Switch (1=Enable) - */ - pci_write_config8(dev, 0x5b, 0x9); - - /* Set 0x58 to 0x42 APIC On and RTC Write Protect.*/ - pci_write_config8(dev, 0x58, 0x42); - - /* Enable serial IRQ, 6PCI clocks. */ - pci_write_config8(dev, 0x52, 0x9); -#else - /* I/O recovery time, default IDE routing */ - pci_write_config8(dev, 0x4c, 0x44); - - /* ROM memory cycles go to LPC. */ - pci_write_config8(dev, 0x59, 0x80); - - /* - * Bit | Meaning - * ------------- - * 3 | Bypass APIC De-Assert Message (1=Enable) - * 2 | APIC HyperTransport Mode (1=Enable) - * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI" - * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch - * 0 | Dynamic Clock Gating Main Switch (1=Enable) - */ - if (cfg && cfg->int_efgh_as_gpio) { - pci_write_config8(dev, 0x5b, 0x9); - } else { - pci_write_config8(dev, 0x5b, 0xb); - } - - /* configure power state of the board after loss of power */ - if (get_option(&pwr_on, "power_on_after_fail") != CB_SUCCESS) - pwr_on = 1; - enables = pci_read_config8(dev, 0x58); - pci_write_config8(dev, 0x58, enables & ~0x02); - outb(0x0d, 0x70); - outb(pwr_on ? 0x00 : 0x80, 0x71); - pci_write_config8(dev, 0x58, enables); - - /* Set 0x58 to 0x43 APIC and RTC. */ - pci_write_config8(dev, 0x58, 0x43); - - /* Enable serial IRQ, 6PCI clocks. */ - pci_write_config8(dev, 0x52, 0x9); -#endif -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - smm_lock(); -#endif - - /* Power management setup */ - setup_pm(dev); - - /* Start the RTC. */ - cmos_init(0); -} - -static void vt8237r_read_resources(struct device *dev) -{ - struct resource *res; - - pci_dev_read_resources(dev); - - /* Fixed ACPI Base IO Base*/ - res = new_resource(dev, 0x88); - res->base = VT8237R_ACPI_IO_BASE; - res->size = 128; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Fixed EISA ECLR I/O Regs */ - res = new_resource(dev, 3); - res->base = 0x4d0; - res->size = 2; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Fixed System Management Bus I/O Resource */ - res = new_resource(dev, 0xD0); - res->base = VT8237R_SMBUS_IO_BASE; - res->size = 16; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Fixed APIC resource */ - res = new_resource(dev, 0x44); - res->base = IO_APIC_ADDR; - res->size = 256; - res->limit = 0xffffffffUL; - res->align = 8; - res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Fixed flashrom resource */ - res = new_resource(dev, 4); - res->base = 0xff000000UL; - res->size = 0x01000000UL; /* 16MB */ - res->limit = 0xffffffffUL; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - res = new_resource(dev, 1); - res->base = 0x0UL; - res->size = 0x1000UL; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static void init_keyboard(struct device *dev) -{ - u8 regval = pci_read_config8(dev, 0x51); - if (regval & 0x1) - pc_keyboard_init(NO_AUX_DEVICE); -} - -static void southbridge_init_common(struct device *dev) -{ - vt8237_common_init(dev); - pci_routing_fixup(dev); - setup_ioapic(VIO_APIC_VADDR, VT8237R_APIC_ID); - setup_i8259(); - init_keyboard(dev); -} - - -static void vt8237_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - pci_write_config16(dev, 0x70, vendor); - pci_write_config16(dev, 0x72, device); -} - -static struct pci_operations lops_pci = { - .set_subsystem = vt8237_set_subsystem, -}; - -static const struct device_operations vt8237r_lpc_ops_s = { - .read_resources = vt8237r_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vt8237s_init, - .scan_bus = scan_lpc_bus, - .ops_pci = &lops_pci, -}; - -static const struct device_operations vt8237r_lpc_ops_r = { - .read_resources = vt8237r_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vt8237r_init, - .scan_bus = scan_lpc_bus, - .ops_pci = &lops_pci, -}; - -static const struct device_operations vt8237r_lpc_ops_a = { - .read_resources = vt8237r_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vt8237a_init, - .scan_bus = scan_lpc_bus, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver lpc_driver_r __pci_driver = { - .ops = &vt8237r_lpc_ops_r, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237R_LPC, -}; - -static const struct pci_driver lpc_driver_a __pci_driver = { - .ops = &vt8237r_lpc_ops_a, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237A_LPC, -}; - -static const struct pci_driver lpc_driver_s __pci_driver = { - .ops = &vt8237r_lpc_ops_s, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237S_LPC, -}; diff --git a/src/southbridge/via/vt8237r/nic.c b/src/southbridge/via/vt8237r/nic.c deleted file mode 100644 index aa6048916a..0000000000 --- a/src/southbridge/via/vt8237r/nic.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz> - * Copyright (C) 2009 Jon Harrison <bothlyn@blueyonder.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "vt8237r.h" - - -static void vt8237_eth_read_resources(struct device *dev) -{ -#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - struct resource *res; - - /* Fix the I/O Resources of the USB2.0 Interface */ - res = new_resource(dev, PCI_BASE_ADDRESS_0); - res->base = 0xF6001000ULL; - res->size = 256; - res->align = 12; - res->gran = 8; - res->limit = res->base + res->size - 1; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_ASSIGNED; -#else - pci_dev_read_resources(dev); -#endif - return; -} - - -static const struct device_operations vt8237_eth_ops = { - .read_resources = vt8237_eth_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver vt8237r_driver_eth __pci_driver = { - .ops = &vt8237_eth_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_8233_7, -}; diff --git a/src/southbridge/via/vt8237r/nvs.h b/src/southbridge/via/vt8237r/nvs.h deleted file mode 100644 index 894bfe89fa..0000000000 --- a/src/southbridge/via/vt8237r/nvs.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <compiler.h> - -typedef struct { - /* Miscellaneous */ - u16 osys; /* 0x00 - Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 prm0; /* 0x03 - SMI function call parameter */ - u8 prm1; /* 0x04 - SMI function call parameter */ - u8 scif; /* 0x05 - SCI function call (via _L00) */ - u8 prm2; /* 0x06 - SCI function call parameter */ - u8 prm3; /* 0x07 - SCI function call parameter */ - u8 lckf; /* 0x08 - Global Lock function for EC */ - u8 prm4; /* 0x09 - Lock function parameter */ - u8 prm5; /* 0x0a - Lock function parameter */ - u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ - u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ - u8 dbgs; /* 0x11 - Debug state */ - u8 linx; /* 0x12 - Linux OS */ - u8 dckn; /* 0x13 - PCIe docking state */ - u8 rsvd[0x28-0x14]; - /* Processor Identification */ - u8 apic; /* 0x28 - APIC enabled */ - u8 mpen; /* 0x29 - MP capable/enabled */ - u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ - u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ - u8 ppcm; /* 0x2c - Max. PPC state */ -} __packed global_nvs_t; diff --git a/src/southbridge/via/vt8237r/pirq.c b/src/southbridge/via/vt8237r/pirq.c deleted file mode 100644 index e7eacdc882..0000000000 --- a/src/southbridge/via/vt8237r/pirq.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com> - * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <pc80/i8259.h> - -#if IS_ENABLED(CONFIG_PIRQ_ROUTE) && IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE) -void pirq_assign_irqs(const unsigned char route[4]) -{ - struct device *pdev; - - pdev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); - if (!pdev) - pdev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); - if (!pdev) - pdev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); - if (!pdev) - return; - - pci_write_config8(pdev, 0x55, route[0] << 4); - pci_write_config8(pdev, 0x56, (route[2] << 4) | route[1]); - pci_write_config8(pdev, 0x57, route[3] << 4); - - /* Enable INT[E-H] mapped to INT[A-D] for simplicity */ - pci_write_config8(pdev, 0x46, 0x00); -} -#endif diff --git a/src/southbridge/via/vt8237r/sata.c b/src/southbridge/via/vt8237r/sata.c deleted file mode 100644 index f09e19072e..0000000000 --- a/src/southbridge/via/vt8237r/sata.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -#define SATA_MISC_CTRL 0x45 - -static void sata_i_init(struct device *dev) -{ - u8 reg; - - printk(BIOS_DEBUG, "Configuring VIA SATA controller\n"); - - /* Class IDE Disk */ - reg = pci_read_config8(dev, SATA_MISC_CTRL); - reg &= 0x7f; /* Sub Class Write Protect off */ - pci_write_config8(dev, SATA_MISC_CTRL, reg); - - /* Change the device class to SATA from RAID. */ - pci_write_config8(dev, PCI_CLASS_DEVICE, 0x1); - reg |= 0x80; /* Sub Class Write Protect on */ - pci_write_config8(dev, SATA_MISC_CTRL, reg); - - return; -} - -static void sata_ii_init(struct device *dev) -{ - u8 reg; - - sata_i_init(dev); - - /* - * Analog black magic, you may or may not need to adjust 0x60-0x6f, - * depends on PCB. - */ - - /* - * Analog PHY - gen1 - * CDR bandwidth [6:5] = 3 - * Squelch Window Select [4:3] = 1 - * CDR Charge Pump [2:0] = 1 - */ - - pci_write_config8(dev, 0x64, 0x49); - - /* Adjust driver current source value to 9. */ - reg = pci_read_config8(dev, 0x65); - reg &= 0xf0; - reg |= 0x9; - pci_write_config8(dev, 0x65, reg); - - /* Set all manual termination 50ohm bits [2:0] and enable [4]. */ - reg = pci_read_config8(dev, 0x6a); - reg |= 0xf; - pci_write_config8(dev, 0x6a, reg); - - /* - * Analog PHY - gen2 - * CDR bandwidth [5:4] = 2 - * Pre / De-emphasis Level [7:6] controls bits [3:2], rest in 0x6e - * CDR Charge Pump [2:0] = 1 - */ - - reg = pci_read_config8(dev, 0x6f); - reg &= 0x08; - reg |= 0x61; - pci_write_config8(dev, 0x6f, reg); - - /* Check if staggered spinup is supported. */ - reg = pci_read_config8(dev, 0x83); - if ((reg & 0x8) == 0) { - /* Start OOB sequence on both drives. */ - reg |= 0x30; - pci_write_config8(dev, 0x83, reg); - } -} - - -static void vt8237_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - pci_write_config16(dev, 0xd4, vendor); - pci_write_config16(dev, 0xd6, device); -} - -static struct pci_operations lops_pci = { - .set_subsystem = vt8237_set_subsystem, -}; - -static const struct device_operations sata_i_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_i_init, - .enable = 0, - .ops_pci = &lops_pci, -}; - -static const struct device_operations sata_ii_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_ii_init, - .enable = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver northbridge_driver_ii __pci_driver = { - .ops = &sata_ii_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237_SATA, -}; - -static const struct pci_driver northbridge_driver_i_a __pci_driver = { - .ops = &sata_i_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237A_SATA, -}; - -static const struct pci_driver northbridge_driver_i __pci_driver = { - .ops = &sata_i_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT6420_SATA, -}; diff --git a/src/southbridge/via/vt8237r/smi.c b/src/southbridge/via/vt8237r/smi.c deleted file mode 100644 index 3af48f9e47..0000000000 --- a/src/southbridge/via/vt8237r/smi.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <cpu/cpu.h> - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* The GDT or coreboot table is going to live here. But a long time - * after we relocated the GNVS, so this is not troublesome. - */ - *(u32 *)0x500 = (u32)gnvs; - *(u32 *)0x504 = (u32)tcg; - *(u32 *)0x508 = (u32)smi1; - outb(0xea, 0xb2); -} diff --git a/src/southbridge/via/vt8237r/smihandler.c b/src/southbridge/via/vt8237r/smihandler.c deleted file mode 100644 index 805c96ea96..0000000000 --- a/src/southbridge/via/vt8237r/smihandler.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/smm.h> -#include <device/pci_def.h> -#include "vt8237r.h" - -#include "nvs.h" - -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; - -/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located - * by coreboot. - */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; -void *tcg = (void *)0x0; -void *smi1 = (void *)0x0; - -#if 0 -/** - * @brief read and clear PM1_STS - * @return PM1_STS register - */ -static u16 reset_pm1_status(void) -{ - u16 reg16; - - reg16 = inw(pmbase + PM1_STS); - /* set status bits are cleared by writing 1 to them */ - outw(reg16, pmbase + PM1_STS); - - return reg16; -} - -static void dump_pm1_status(u16 pm1_sts) -{ - printk(BIOS_SPEW, "PM1_STS: "); - if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK "); - if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR "); - if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC "); - if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN "); - if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL "); - if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM "); - if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF "); - printk(BIOS_SPEW, "\n"); - int reg16 = inw(pmbase + PM1_EN); - printk(BIOS_SPEW, "PM1_EN: %x\n", reg16); -} -#endif - -/** - * @brief read and clear SMI_STS - * @return SMI_STS register - */ -static u16 reset_smi_status(void) -{ - u16 reg16; - - reg16 = inw(pmbase + SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outw(reg16, pmbase + SMI_STS); - - return reg16; -} - -static void dump_smi_status(u16 smi_sts) -{ - printk(BIOS_DEBUG, "SMI_STS: "); - if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "GPIO_RANGE_1 "); - if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "GPIO_RANGE_0 "); - if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "GP3_TIMEOUT "); - if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "GP2_TIMEOUT "); - if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "SERR_IRQ "); - if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "PMIO_5 "); - if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "THRMTRIP# "); - if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "CLKRUN# "); - if (smi_sts & (1 << 7)) printk(BIOS_DEBUG, "PRIMARY_IRQ/NMI/SMI "); - if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI "); - if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "BIOS_STATUS "); - if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "LEGACY_USB "); - if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "GP1_TIMEOUT "); - if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "GP0_TIMEOUT "); - if (smi_sts & (1 << 1)) printk(BIOS_DEBUG, "SECONDARY_EVENT_TIMEOUT "); - if (smi_sts & (1 << 0)) printk(BIOS_DEBUG, "PRIMARY_ACTIVITY "); - printk(BIOS_DEBUG, "\n"); -} - -int southbridge_io_trap_handler(int smif) -{ - switch (smif) { - case 0x32: - printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: - * On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - */ - gnvs->smif = 0; - return 1; /* IO trap handled */ - } - - /* Not handled */ - return 0; -} - -/** - * @brief Set the EOS bit - */ -void southbridge_smi_set_eos(void) -{ - u8 reg8; - - reg8 = inb(pmbase + SMI_EN); - reg8 |= EOS; - outb(reg8, pmbase + SMI_EN); -} - -static void southbridge_smi_cmd(unsigned int node, smm_state_save_area_t *state_save) -{ - u16 pmctrl; - u8 reg8; - - reg8 = inb(pmbase + 0x2f); - switch (reg8) { - case APM_CNT_CST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - printk(BIOS_DEBUG, "C-state control\n"); - break; - case APM_CNT_PST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - printk(BIOS_DEBUG, "P-state control\n"); - break; - case APM_CNT_ACPI_DISABLE: - pmctrl = inw(pmbase + PM1_CNT); - pmctrl &= ~SCI_EN; - outw(pmctrl, pmbase + PM1_CNT); - printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); - break; - case APM_CNT_ACPI_ENABLE: - pmctrl = inw(pmbase + PM1_CNT); - pmctrl |= SCI_EN; - outw(pmctrl, pmbase + PM1_CNT); - printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); - break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); - return; - } - gnvs = *(global_nvs_t **)0x500; - tcg = *(void **)0x504; - smi1 = *(void **)0x508; - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1); - break; - default: - printk(BIOS_DEBUG, "SMI#: Unknown function SMI_CMD=%02x\n", reg8); - } -} - -typedef void (*smi_handler_t)(unsigned int node, - smm_state_save_area_t *state_save); - -smi_handler_t southbridge_smi[32] = { - NULL, // [0] - NULL, // [1] - NULL, // [2] - NULL, // [3] - NULL, // [4] - NULL, // [5] - southbridge_smi_cmd, // [6] - NULL, // [7] - NULL, // [8] - NULL, // [9] - NULL, // [10] - NULL, // [11] - NULL, // [12] - NULL, // [13] - NULL, // [14] - NULL, // [15] -}; - -/** - * @brief Interrupt handler for SMI# - * - * @param node - * @param state_save revision of the smm state save map - */ - -void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) -{ - int i, dump = 0; - u32 smi_sts; - - /* Update global variable pmbase */ - pmbase = pci_read_config16(PCI_DEV(0, 0x11, 0), 0x88) & 0xfffc; - - /* We need to clear the SMI status registers, or we won't see what's - * happening in the following calls. - */ - smi_sts = reset_smi_status(); - - /* Filter all non-enabled SMI events */ - // FIXME Double check, this clears MONITOR - // smi_sts &= inl(pmbase + SMI_EN); - - /* Call SMI sub handler for each of the status bits */ - for (i = 0; i < 16; i++) { - if (smi_sts & (1 << i)) { - if (southbridge_smi[i]) - southbridge_smi[i](node, state_save); - else { - printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no " - "handler available.\n", i); - dump = 1; - } - } - } - - if (dump) { - dump_smi_status(smi_sts); - } - -} diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c deleted file mode 100644 index 42a0afe4a5..0000000000 --- a/src/southbridge/via/vt8237r/usb.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz> - * Copyright (C) 2009 Jon Harrison <bothlyn@blueyonder.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "chip.h" -#include "vt8237r.h" - -#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) -u32 usb_io_addr[4] = {0xcc00, 0xd000, 0xd400, 0xd800}; -#endif - -static void usb_i_init(struct device *dev) -{ -#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - u8 reg8; - - printk(BIOS_DEBUG, "Entering %s\n", __func__); - - reg8 = pci_read_config8(dev, 0x04); - - printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8); - - reg8 = reg8 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, 0x04, reg8); - - printk(BIOS_SPEW, "%s Wrote %02X to PCI Command Reg\n", dev_path(dev), reg8); - - /* Set Cache Line Size and Latency Timer */ - pci_write_config8(dev, 0x0c, 0x08); - pci_write_config8(dev, 0x0d, 0x20); - - /* Enable Sub Device ID Back Door and set Generic */ - reg8 = pci_read_config8(dev, 0x42); - reg8 |= 0x10; - pci_write_config8(dev, 0x42, reg8); - pci_write_config16(dev, 0x2e, 0xAA07); - reg8 &= ~0x10; - pci_write_config8(dev, 0x42, reg8); - - - pci_write_config8(dev, 0x41, 0x12); - - pci_write_config8(dev, 0x49, 0x0B); - - /* Clear PCI Status */ - pci_write_config16(dev, 0x06, 0x7A10); -#endif - return; -} - -static void vt8237_usb_i_read_resources(struct device *dev) -{ -#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - struct resource *res; - u8 function = (u8) dev->path.pci.devfn & 0x7; - - printk(BIOS_SPEW, "VT8237R Fixing USB 1.1 fn %d I/O resource = 0x%04X\n", function, usb_io_addr[function]); - - /* Fix the I/O Resources of the USB1.1 Interfaces */ - /* Auto PCI probe seems to size the resources */ - /* Incorrectly */ - res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = usb_io_addr[function]; - res->size = 256; - res->limit = 0xffffUL; - res->align = 10; - res->gran = 8; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | - IORESOURCE_ASSIGNED; -#else - pci_dev_read_resources(dev); -#endif - return; -} - -static void usb_ii_init(struct device *dev) -{ - struct southbridge_via_vt8237r_config *cfg; -#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - u8 reg8; - - printk(BIOS_DEBUG, "Entering %s\n", __func__); - - /* Set memory Write and Invalidate */ - reg8 = pci_read_config8(dev, 0x04); - reg8 |= 0x10; - pci_write_config8(dev, 0x04, reg8); - - /* Set Cache line Size and Latency Timer */ - pci_write_config8(dev, 0x0c, 0x08); - pci_write_config8(dev, 0x0d, 0x20); - - /* Clear PCI Status */ - pci_write_config16(dev, 0x06, 0x7A10); -#endif - - cfg = dev->chip_info; - - if (cfg) { - if (cfg->usb2_termination_set) { - /* High Speed Port Pad Termination Resistor Fine Tune */ - pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | - (cfg->usb2_termination_d << 4)); - pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | - (cfg->usb2_termination_b << 4)); - pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | - (cfg->usb2_termination_f << 4)); - pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | - (cfg->usb2_termination_h << 4)); - } - - if (cfg->usb2_dpll_set) { - /* Delay DPLL Input Data Control */ - pci_write_config8(dev, 0x5c, - (pci_read_config8(dev, 0x5c) & ~0x70) | - (cfg->usb2_dpll_delay << 4)); - } - } -} - -static void vt8237_usb_ii_read_resources(struct device *dev) -{ -#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) - struct resource *res; - - /* Fix the I/O Resources of the USB2.0 Interface */ - res = new_resource(dev, PCI_BASE_ADDRESS_0); - res->base = 0xF6000000ULL; - res->size = 256; - res->align = 12; - res->gran = 8; - res->limit = res->base + res->size - 1; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_ASSIGNED; -#else - pci_dev_read_resources(dev); -#endif - return; -} - -static void vt8237_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - pci_write_config32(dev, 0x42, pci_read_config32(dev, 0x42) | 0x10); - pci_write_config16(dev, 0x2c, vendor); - pci_write_config16(dev, 0x2e, device); - pci_write_config32(dev, 0x42, pci_read_config32(dev, 0x42) & ~0x10); -} - -static struct pci_operations lops_pci = { - .set_subsystem = vt8237_set_subsystem, -}; - -static const struct device_operations usb_i_ops = { - .read_resources = vt8237_usb_i_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_i_init, - .enable = 0, - .ops_pci = &lops_pci, -}; - -static const struct device_operations usb_ii_ops = { - .read_resources = vt8237_usb_ii_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_ii_init, - .enable = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver vt8237r_driver_usbii __pci_driver = { - .ops = &usb_ii_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237R_EHCI, -}; - -static const struct pci_driver vt8237r_driver_usbi __pci_driver = { - .ops = &usb_i_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237R_UHCI, -}; diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c deleted file mode 100644 index b88affee84..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "vt8237r.h" -#include "chip.h" - -/* - * Datasheet: http://www.via.com.tw/en/downloads/datasheets/chipsets/ - * VT8237R_SouthBridge_Revision2.06_Lead-Free.zip - */ - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 7 -void writeback(struct device *dev, u16 where, u8 what) -{ - u8 regval; - - pci_write_config8(dev, where, what); - regval = pci_read_config8(dev, where); - - if (regval != what) - printk(BIOS_DEBUG, "Writeback to %02x failed %02x\n", - where, regval); -} -#else -void writeback(struct device *dev, u16 where, u8 what) -{ - pci_write_config8(dev, where, what); -} -#endif - -void dump_south(struct device *dev) -{ - int i, j; - - for (i = 0; i < 256; i += 16) { - printk(BIOS_DEBUG, "%02x:", i); - for (j = 0; j < 16; j++) - printk(BIOS_DEBUG, " %02x", pci_read_config8(dev, i + j)); - printk(BIOS_DEBUG, "\n"); - } -} - -static void vt8237r_enable(struct device *dev) -{ - u16 vid, did; - struct southbridge_via_vt8237r_config *sb = - (struct southbridge_via_vt8237r_config *)dev->chip_info; - - if (dev->path.type == DEVICE_PATH_PCI) { - vid = pci_read_config16(dev, PCI_VENDOR_ID); - did = pci_read_config16(dev, PCI_DEVICE_ID); - if (vid == PCI_VENDOR_ID_VIA && - (did == PCI_DEVICE_ID_VIA_VT8237R_LPC || - did == PCI_DEVICE_ID_VIA_VT8237A_LPC || - did == PCI_DEVICE_ID_VIA_VT8237S_LPC)) { - pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); - pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); - } - } - - /* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */ -} - -struct chip_operations southbridge_via_vt8237r_ops = { - CHIP_NAME("VIA VT8237R Southbridge") - .enable_dev = vt8237r_enable, -}; diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h deleted file mode 100644 index f383736504..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_VIA_VT8237R_VT8237R_H -#define SOUTHBRIDGE_VIA_VT8237R_VT8237R_H - -#include <compiler.h> - -/* Static resources for the VT8237R southbridge */ - -#define VT8237R_APIC_ID 0x2 -#define VT8237R_ACPI_IO_BASE 0x500 -#define DEFAULT_PMBASE VT8237R_ACPI_IO_BASE -#define VT8237R_SMBUS_IO_BASE 0x400 -/* 0x0 disabled, 0x2 reserved, 0xf = IRQ15 */ -#define VT8237R_ACPI_IRQ 0x9 -#define VT8237S_SPI_MEM_BASE 0xfed02000UL - -/* PMBASE FIXME mostly taken from ich7 */ -#define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) -#define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) -#define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) -#define PM1_TMR 0x08 -#define PROC_CNT 0x10 -#define LV2 0x14 -#define LV3 0x15 -#define SMI_STS 0x28 -#define SMI_EN 0x2d -#define EOS (1 << 0) - -/* IDE */ -#define IDE_CS 0x40 -#define IDE_CONF_I 0x41 -#define IDE_CONF_II 0x42 -#define IDE_CONF_FIFO 0x43 -#define IDE_MISC_I 0x44 -#define IDE_MISC_II 0x45 -#define IDE_UDMA 0x50 - -#define VT8237R_IDE0_80PIN_CABLE ((1UL<<28)|(1UL<<20)) -#define VT8237R_IDE1_80PIN_CABLE ((1UL<<12)|(1UL<< 4)) -#define VT8237R_IDE_CABLESEL_MASK (VT8237R_IDE0_80PIN_CABLE|VT8237R_IDE1_80PIN_CABLE) - -/* SMBus */ -#define VT8237R_PSON 0x82 -#define VT8237R_POWER_WELL 0x94 -#define VT8237R_SMBUS_IO_BASE_REG 0xd0 -#define VT8237R_SMBUS_HOST_CONF 0xd2 - -#define SMBHSTSTAT (VT8237R_SMBUS_IO_BASE + 0x0) -#define SMBSLVSTAT (VT8237R_SMBUS_IO_BASE + 0x1) -#define SMBHSTCTL (VT8237R_SMBUS_IO_BASE + 0x2) -#define SMBHSTCMD (VT8237R_SMBUS_IO_BASE + 0x3) -#define SMBXMITADD (VT8237R_SMBUS_IO_BASE + 0x4) -#define SMBHSTDAT0 (VT8237R_SMBUS_IO_BASE + 0x5) - -#define HOST_RESET 0xff -/* 1 in the 0 bit of SMBHSTADD states to READ. */ -#define READ_CMD 0x01 -#define SMBUS_TIMEOUT (100 * 1000 * 10) -#define I2C_TRANS_CMD 0x40 -#define CLOCK_SLAVE_ADDRESS 0x69 - -#if IS_ENABLED(CONFIG_DEBUG_SMBUS) -#define PRINT_DEBUG(x) printk(BIOS_DEBUG, x) -#define PRINT_DEBUG_HEX16(x) printk(BIOS_DEBUG, "%04x", x) -#else -#define PRINT_DEBUG(x) -#define PRINT_DEBUG_HEX16(x) -#endif - -#define SMBUS_DELAY() inb(0x80) - -struct vt8237_network_rom { - u8 mac_address[6]; - u8 phy_addr; - u8 res1; - u16 sub_sid; - u16 sub_vid; - u16 pid; - u16 vid; - u8 pmcc; - u8 data_sel; - u8 pmu_data_reg; - u8 aux_curr; - u16 reserved; - u8 min_gnt; - u8 max_lat; - u8 bcr0; - u8 bcr1; - u8 cfg_a; - u8 cfg_b; - u8 cfg_c; - u8 cfg_d; - u8 checksum; -} __packed; - -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 -#define MAINBOARD_POWER_KEEP 2 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - - -#ifdef __PRE_RAM__ -u8 smbus_read_byte(u8 dimm, u8 offset); -void smbus_write_byte(u8 dimm, u8 offset, u8 data); -void enable_smbus(void); -void smbus_fixup(const u8 channel0[], int ram_slots); -void vt8237_sb_enable_fid_vid(void); -void enable_rom_decode(void); -void vt8237_early_spi_init(void); -int vt8237_early_network_init(struct vt8237_network_rom *rom); -#else -void writeback(struct device *dev, u16 where, u8 what); -void dump_south(struct device *dev); -u32 vt8237_ide_80pin_detect(struct device *dev); -#endif - -#endif |