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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-03-20 17:52:24 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-03-21 16:20:02 +0000
commit00bb441ba4f9d427901043db0bb686d389e3adca (patch)
tree3b4736fcd984508c93c1eb1a20f3408b2d8801f0 /src/southbridge
parent15ccbf042ddda877cde23e9b0d5d3f5256e62c33 (diff)
downloadcoreboot-00bb441ba4f9d427901043db0bb686d389e3adca.tar.xz
sb/intel/lynxpoint: Remove PCI bridge function
Legacy PCI-to-PCI (parallel) bridge 0:1e.0 is no longer supported in these SKUs. Change-Id: I954ee9cf8228c6352743cae968a0dd665865496c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/lynxpoint/Makefile.inc1
-rw-r--r--src/southbridge/intel/lynxpoint/pci.c137
2 files changed, 0 insertions, 138 deletions
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index c2a49fdea6..b18e6dafc8 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -18,7 +18,6 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
ramstage-y += pch.c
ramstage-y += azalia.c
ramstage-y += lpc.c
-ramstage-y += pci.c
ramstage-y += pcie.c
ramstage-y += sata.c
ramstage-y += usb_ehci.c
diff --git a/src/southbridge/intel/lynxpoint/pci.c b/src/southbridge/intel/lynxpoint/pci.c
deleted file mode 100644
index 6c26bb8e40..0000000000
--- a/src/southbridge/intel/lynxpoint/pci.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include "pch.h"
-
-static void pci_init(struct device *dev)
-{
- u16 reg16;
- u8 reg8;
-
- printk(BIOS_DEBUG, "PCI init.\n");
- /* Enable Bus Master */
- reg16 = pci_read_config16(dev, PCI_COMMAND);
- reg16 |= PCI_COMMAND_MASTER;
- pci_write_config16(dev, PCI_COMMAND, reg16);
-
- /* This device has no interrupt */
- pci_write_config8(dev, INTR, 0xff);
-
- /* disable parity error response and SERR */
- reg16 = pci_read_config16(dev, BCTRL);
- reg16 &= ~(1 << 0);
- reg16 &= ~(1 << 1);
- pci_write_config16(dev, BCTRL, reg16);
-
- /* Master Latency Count must be set to 0x04! */
- reg8 = pci_read_config8(dev, SMLT);
- reg8 &= 0x07;
- reg8 |= (0x04 << 3);
- pci_write_config8(dev, SMLT, reg8);
-
- /* Will this improve throughput of bus masters? */
- pci_write_config8(dev, PCI_MIN_GNT, 0x06);
-
- /* Clear errors in status registers */
- reg16 = pci_read_config16(dev, PSTS);
- //reg16 |= 0xf900;
- pci_write_config16(dev, PSTS, reg16);
-
- reg16 = pci_read_config16(dev, SECSTS);
- // reg16 |= 0xf900;
- pci_write_config16(dev, SECSTS, reg16);
-}
-
-static void ich_pci_dev_enable_resources(struct device *dev)
-{
- const struct pci_operations *ops;
- uint16_t command;
-
- /* Set the subsystem vendor and device id for mainboard devices */
- ops = ops_pci(dev);
- if (dev->on_mainboard && ops && ops->set_subsystem) {
- printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
- dev_path(dev),
- CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
- ops->set_subsystem(dev,
- CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
- }
-
- command = pci_read_config16(dev, PCI_COMMAND);
- command |= dev->command;
- /* If we write to PCI_COMMAND, on some systems
- * this will cause the ROM and APICs not being visible
- * anymore.
- */
- printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
- pci_write_config16(dev, PCI_COMMAND, command);
-}
-
-static void ich_pci_bus_enable_resources(struct device *dev)
-{
- uint16_t ctrl;
- /* enable IO in command register if there is VGA card
- * connected with (even it does not claim IO resource)
- */
- if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
- dev->command |= PCI_COMMAND_IO;
- ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
- ctrl |= dev->link_list->bridge_ctrl;
- ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
- printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
- pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
-
- /* This is the reason we need our own pci_bus_enable_resources */
- ich_pci_dev_enable_resources(dev);
-}
-
-static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
-{
- /* NOTE: This is not the default position! */
- if (!vendor || !device) {
- pci_write_config32(dev, 0x54,
- pci_read_config32(dev, PCI_VENDOR_ID));
- } else {
- pci_write_config32(dev, 0x54,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
- }
-}
-
-static struct pci_operations pci_ops = {
- .set_subsystem = set_subsystem,
-};
-
-static struct device_operations device_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = ich_pci_bus_enable_resources,
- .init = pci_init,
- .scan_bus = pci_scan_bridge,
- .ops_pci = &pci_ops,
-};
-
-static const struct pci_driver pch_pci __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x2448,
-};