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authorBruce Griffith <Bruce.Griffith@se-eng.com>2013-06-25 14:29:08 -0600
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-06-28 01:37:51 +0200
commit01677b6625bff61b6abc570cf7aec3146c7a8d47 (patch)
tree3b520f799f59df404746afeb58c5f270ab0c14ff /src/southbridge
parent53abac1767c5c40ce0eafe729cd04cca1fcc8292 (diff)
downloadcoreboot-01677b6625bff61b6abc570cf7aec3146c7a8d47.tar.xz
amd/cimx/sb700/late.c: Add type cast to (UINT8)
This change inserts a type cast to eliminate a compiler warning. Change-Id: If223f61f1565caeadb1b7e0762975b1b2412eda5 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3541 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cimx/sb700/late.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index ede9fb3a01..b259a7b797 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -254,7 +254,7 @@ static void sb700_enable(device_t dev)
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1)
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
- setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
+ setup_ioapic(ioapic_base, (UINT8) (CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS));
#elif (CONFIG_APIC_ID_OFFSET > 0)
/* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
setup_ioapic(ioapic_base, 0);