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| author | Marc Jones <marc.jones@se-eng.com> | 2013-02-11 14:39:28 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-17 22:49:34 +0100 |
| commit | 058d70f163e1a46e16d8577de4e612af04b9aeca (patch) | |
| tree | 6ceae6d8581504828c9e8bbd6721c811b7bb9842 /src/southbridge | |
| parent | 783f226208f0d25cc25ff3a9d56e108a09fb4cff (diff) | |
| download | coreboot-058d70f163e1a46e16d8577de4e612af04b9aeca.tar.xz | |
Add bd82x6x XHCI(USB3) S3/S4 workaround
The bd82x6x requires some additional setting on S3/S4 entry.
Change-Id: I24489ab94dd7cd5a4a64044f25153f5b01a45b77
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2759
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/smihandler.c | 45 |
1 files changed, 40 insertions, 5 deletions
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 093da5c60a..5d5dad1460 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -328,15 +328,50 @@ static void southbridge_gate_memory_reset(void) static void xhci_sleep(u8 slp_typ) { - u32 reg32; + u32 reg32, xhci_bar; + u16 reg16; - if (slp_typ == SLP_TYP_S5) { - reg32 = pcie_read_config32(PCH_XHCI_DEV, 0x74); - reg32 |= (1 << 8 | 0x03 ); - pcie_write_config32(PCH_XHCI_DEV, 0x74, reg32); + switch (slp_typ) { + case SLP_TYP_S3: + case SLP_TYP_S4: + reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74); + reg16 &= ~0x03UL; + pcie_write_config32(PCH_XHCI_DEV, 0x74, reg16); + + reg32 = pcie_read_config32(PCH_XHCI_DEV, PCI_COMMAND); + reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pcie_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); + + xhci_bar = pcie_read_config32(PCH_XHCI_DEV, + PCI_BASE_ADDRESS_0) & ~0xFUL; + + if ((xhci_bar + 0x4C0) & 1) + pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); + if ((xhci_bar + 0x4D0) & 1) + pch_iobp_update(0xEC000182, ~0UL, (3 << 2)); + if ((xhci_bar + 0x4E0) & 1) + pch_iobp_update(0xEC000282, ~0UL, (3 << 2)); + if ((xhci_bar + 0x4F0) & 1) + pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); + + reg32 = pcie_read_config32(PCH_XHCI_DEV, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pcie_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); + + reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74); + reg16 |= 0x03; + pcie_write_config16(PCH_XHCI_DEV, 0x74, reg16); + break; + + case SLP_TYP_S5: + reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74); + reg16 |= ((1 << 8) | 0x03); + pcie_write_config16(PCH_XHCI_DEV, 0x74, reg16); + break; } } + static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) { u8 reg8; |