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| author | Dennis Wassenberg <dennis.wassenberg@secunet.com> | 2015-09-10 12:03:45 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2016-12-08 01:35:22 +0100 |
| commit | 0c04720cb764bc21e15f85bc4e0ae3310f933ae3 (patch) | |
| tree | d8c75c4bdc30109a3ef203a33978858dc54a4043 /src/southbridge | |
| parent | f8960a6149578172d37c3223e5309da2d14f3da6 (diff) | |
| download | coreboot-0c04720cb764bc21e15f85bc4e0ae3310f933ae3.tar.xz | |
sb/intel/bd82x6x: Add TCO_Lock in finalize step
CHIPSEC found that the TCO_Lock was not set.
This is used to prevent changing the TCO_EN bit.
Change-Id: I42364dbef2511e656662566cf94591e76c6847ed
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Reviewed-on: https://review.coreboot.org/17351
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/finalize.c | 10 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 3 |
2 files changed, 13 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index 90932e16bc..c9296fd949 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -16,11 +16,15 @@ #include <arch/io.h> #include <console/post_codes.h> +#include <cpu/x86/smm.h> #include "pch.h" #include <spi-generic.h> void intel_pch_finalize_smm(void) { + u16 tco1_cnt; + u16 pmbase; + if (CONFIG_LOCK_SPI_ON_RESUME_RO || CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS) { /* Copy flash regions from FREG0-4 to PR0-4 and enable write protection bit31 */ @@ -66,6 +70,12 @@ void intel_pch_finalize_smm(void) pci_write_config32(PCI_DEV(0, 27, 0), 0x74, pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); + /* TCO_Lock */ + pmbase = smm_get_pmbase(); + tco1_cnt = inw(pmbase + TCO1_CNT); + tco1_cnt |= TCO_LOCK; + outw(tco1_cnt, pmbase + TCO1_CNT); + /* Indicate finalize step with post code */ outb(POST_OS_BOOT, 0x80); } diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 1977c8f9d2..8b22fca334 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -534,6 +534,9 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 +#define TCO1_CNT 0x68 +#define TCO_LOCK (1 << 12) +#define TCO2_CNT 0x6a /* * SPI Opcode Menu setup for SPIBAR lockdown |