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authorElyes HAOUAS <ehaouas@noos.fr>2019-02-05 08:24:00 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-02-07 08:53:07 +0000
commit0c152cf1bbc3673d80f255fcc102d5784e0974c1 (patch)
tree70b0b350512a03931763dc94749c54afad84b830 /src/southbridge
parenta08765d2871b891c8da2e8686a0db35b320c96b0 (diff)
downloadcoreboot-0c152cf1bbc3673d80f255fcc102d5784e0974c1.tar.xz
src: Remove unused include device/pnp_def.h
Change-Id: Ibb7ce42588510dc5ffb04c950c4c8c64e9a2fa37 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/fsp_rangeley/romstage.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 0032fd6715..ec60920ac5 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -20,7 +20,6 @@
#include <timestamp.h>
#include <arch/io.h>
#include <device/pci_def.h>
-#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <cbmem.h>
#include <console/console.h>