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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-06-29 16:17:33 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-07-14 19:42:49 +0200
commit1110495de926db4b21b9969da522e5270c67f115 (patch)
tree04a04b6e797173c1b3639a4c4ecb90c544ab84ab /src/southbridge
parent77d1280d0c866a9f85e62f74c43fe8d021a4ff39 (diff)
downloadcoreboot-1110495de926db4b21b9969da522e5270c67f115.tar.xz
SPI: Split writes using spi_crop_chunk()
SPI controllers in Intel and AMD bridges have a slightly different restriction on how long transactions they can handle. Change-Id: I3d149d4b7e7e9633482a153d5e380a86c553d871 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6163 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/agesa/hudson/spi.c6
-rw-r--r--src/southbridge/amd/cimx/sb800/spi.c7
-rw-r--r--src/southbridge/intel/common/spi.c7
3 files changed, 19 insertions, 1 deletions
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index 720b26f83e..f050a63f91 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -42,6 +42,7 @@ static int bus_claimed = 0;
#define SPI_REG_CNTRL11 0xd
#define CNTRL11_FIFOPTR_MASK 0x07
+#define AMD_SB_SPI_TX_LEN 64
static u32 spibar;
@@ -86,6 +87,11 @@ void spi_init(void)
spibar = pci_read_config32(dev, 0xA0) & ~0x1F;
}
+unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
+{
+ return min(AMD_SB_SPI_TX_LEN - cmd_len, buf_len);
+}
+
int spi_xfer(struct spi_slave *slave, const void *dout,
unsigned int bytesout, void *din, unsigned int bytesin)
{
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
index a46349e933..e5b2407082 100644
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ b/src/southbridge/amd/cimx/sb800/spi.c
@@ -32,6 +32,8 @@
static int bus_claimed = 0;
#endif
+#define AMD_SB_SPI_TX_LEN 8
+
static u32 spibar;
static void reset_internal_fifo_pointer(void)
@@ -56,6 +58,11 @@ void spi_init()
spibar = pci_read_config32(dev, 0xA0) & ~0x1F;
}
+unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
+{
+ return min(AMD_SB_SPI_TX_LEN - cmd_len, buf_len);
+}
+
int spi_xfer(struct spi_slave *slave, const void *dout,
unsigned int bytesout, void *din, unsigned int bytesin)
{
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 76fd22691f..8e7192b49f 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -550,6 +550,11 @@ static int spi_is_multichip (void)
return !!((cntlr.flmap0 >> 8) & 3);
}
+unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
+{
+ return min(cntlr.databytes, buf_len);
+}
+
int spi_xfer(struct spi_slave *slave, const void *dout,
unsigned int bytesout, void *din, unsigned int bytesin)
{
@@ -639,7 +644,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
*/
if (trans.bytesout > cntlr.databytes) {
printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"
- " CONTROLLER_PAGE_LIMIT?\n");
+ " spi_crop_chunk()?\n");
return -1;
}