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authorSven Schnelle <svens@stackframe.org>2012-06-20 14:54:08 +0200
committerSven Schnelle <svens@stackframe.org>2012-06-23 10:05:01 +0200
commit1f20da7c3350bf8a0830c579f28fddc74af3f074 (patch)
tree0072e44f090d508c77c28f465afe7ee9b0c47ade /src/southbridge
parente4cece0d6f3bfa7254600e6fd4b5245733a02d44 (diff)
downloadcoreboot-1f20da7c3350bf8a0830c579f28fddc74af3f074.tar.xz
i3100: add smbus_write_byte()
Required for Supermicro X7DB8, which needs the FBDIMM clock generator setup during romstage. Change-Id: I30ca8354087e851487aee0614595782131d4d9bc Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1116 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i3100/early_smbus.c7
-rw-r--r--src/southbridge/intel/i3100/smbus.c14
-rw-r--r--src/southbridge/intel/i3100/smbus.h43
3 files changed, 63 insertions, 1 deletions
diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c
index f3d4450c5e..035c0a9cfd 100644
--- a/src/southbridge/intel/i3100/early_smbus.c
+++ b/src/southbridge/intel/i3100/early_smbus.c
@@ -37,7 +37,12 @@ static void enable_smbus(void)
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
}
-static int smbus_read_byte(u32 device, u32 address)
+static __attribute__((unused)) int smbus_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
+
+static __attribute__((unused)) int smbus_write_byte(unsigned device, u8 address, u8 data)
+{
+ return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data);
+}
diff --git a/src/southbridge/intel/i3100/smbus.c b/src/southbridge/intel/i3100/smbus.c
index 23602acb21..c11237ae8d 100644
--- a/src/southbridge/intel/i3100/smbus.c
+++ b/src/southbridge/intel/i3100/smbus.c
@@ -41,8 +41,22 @@ static int lsmbus_read_byte(device_t dev, u8 address)
return do_smbus_read_byte(res->base, device, address);
}
+static int lsmbus_write_byte(device_t dev, u8 address, u8 byte)
+{
+ u16 device;
+ struct resource *res;
+ struct bus *pbus;
+
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
+ res = find_resource(pbus->dev, 0x20);
+
+ return do_smbus_write_byte(res->base, device, address, byte);
+}
+
static struct smbus_bus_operations lops_smbus_bus = {
.read_byte = lsmbus_read_byte,
+ .write_byte = lsmbus_write_byte,
};
static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/intel/i3100/smbus.h b/src/southbridge/intel/i3100/smbus.h
index 7023a5b751..478974eff7 100644
--- a/src/southbridge/intel/i3100/smbus.h
+++ b/src/southbridge/intel/i3100/smbus.h
@@ -110,3 +110,46 @@ static int do_smbus_read_byte(u32 smbus_io_base, u16 device, u8 address)
}
return byte;
}
+
+static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned address, unsigned data)
+{
+ unsigned char global_status_register;
+
+ if (smbus_wait_until_ready(smbus_base) < 0)
+ return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+ /* Setup transaction */
+ /* Disable interrupts */
+ outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+ /* Set the device I'm talking too */
+ outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
+ /* Set the command/address... */
+ outb(address & 0xff, smbus_base + SMBHSTCMD);
+ /* Set up for a byte data read */
+ outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+ (smbus_base + SMBHSTCTL));
+ /* Clear any lingering errors, so the transaction will run */
+ outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+ /* Clear the data byte... */
+ outb(data, smbus_base + SMBHSTDAT0);
+
+ /* Start the command */
+ outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+ smbus_base + SMBHSTCTL);
+
+ /* Poll for transaction completion */
+ if (smbus_wait_until_done(smbus_base) < 0)
+ return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+
+ global_status_register = inb(smbus_base + SMBHSTSTAT);
+
+ /* Ignore the "In Use" status... */
+ global_status_register &= ~(3 << 5);
+
+ /* Read results of transaction */
+ if (global_status_register != (1 << 1))
+ return SMBUS_ERROR;
+
+ return 0;
+}