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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-11-23 18:54:34 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-28 01:03:34 +0100 |
| commit | 2220f0d7c79b2f22ccdc93e8fa643e8928c1ff3c (patch) | |
| tree | 52c354aaf8d8eeb7ef031d40b332863cdcf7bf5d /src/southbridge | |
| parent | 1b593e5ad76bb66298c6f39b2cfb6fdf1f784c38 (diff) | |
| download | coreboot-2220f0d7c79b2f22ccdc93e8fa643e8928c1ff3c.tar.xz | |
sb/ricoh/rl5c476/rl5c476.c: Use tab for indents
Change-Id: I3967d1ff0623037efa66927843e0c47f408832d7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17582
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/ricoh/rl5c476/rl5c476.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 78561cc15b..2a73ab13a7 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -163,9 +163,9 @@ static void rl5c476_read_resources(device_t dev) struct resource *resource; - /* For CF socket we need an extra memory window for - * the control structure of the CF itself - */ + /* For CF socket we need an extra memory window for + * the control structure of the CF itself + */ if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ /* fake index as it isn't in PCI config space */ resource = new_resource(dev, 1); @@ -196,18 +196,18 @@ static void rl5c476_set_resources(device_t dev) static void rl5c476_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - u16 miscreg = pci_read_config16(dev, 0x82); - /* Enable subsystem id register writes */ - pci_write_config16(dev, 0x82, miscreg | 0x40); - - pci_write_config16(dev, 0x40, vendor); - pci_write_config16(dev, 0x42, device); - /* restore original contents */ - pci_write_config16(dev, 0x82, miscreg); + u16 miscreg = pci_read_config16(dev, 0x82); + /* Enable subsystem id register writes */ + pci_write_config16(dev, 0x82, miscreg | 0x40); + + pci_write_config16(dev, 0x40, vendor); + pci_write_config16(dev, 0x42, device); + /* restore original contents */ + pci_write_config16(dev, 0x82, miscreg); } static struct pci_operations rl5c476_pci_ops = { - .set_subsystem = rl5c476_set_subsystem, + .set_subsystem = rl5c476_set_subsystem, }; static struct device_operations ricoh_rl5c476_ops = { |