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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-04-16 16:30:00 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-04-20 20:03:26 +0200
commit29c3e367da8f80becacb66193d044f90b49bf0c5 (patch)
treed6685869852c4346be65be39ae3034f45988a565 /src/southbridge
parentb1ccccc2073c40f622f5c0b2e861c3e8453a94f9 (diff)
downloadcoreboot-29c3e367da8f80becacb66193d044f90b49bf0c5.tar.xz
AMD cimx sb700/sb800/sb900: Fix NODE_PCI and use of MAX_PHYSICAL_CPUS
Match the definition of NODE_PCI() with get_node_pci(), so romstage and ramstage agree of the PCI BDFs for nodes. Note that all board have CONFIG_CDB = 0x18 and the maximum for nodes = 8, so we always have (CONFIG_CDB + x) < 32. Change-Id: I676ee53a65ef5b1243df2c5889577dd987c8fc9c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cimx/sb700/reset.c6
-rw-r--r--src/southbridge/amd/cimx/sb800/reset.c6
-rw-r--r--src/southbridge/amd/cimx/sb900/reset.c6
3 files changed, 3 insertions, 15 deletions
diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c
index 16c56a2c83..a00fc15653 100644
--- a/src/southbridge/amd/cimx/sb700/reset.c
+++ b/src/southbridge/amd/cimx/sb700/reset.c
@@ -26,11 +26,7 @@
#define HT_INIT_CONTROL 0x6C
#define HTIC_BIOSR_Detect (1<<5)
-#if CONFIG_MAX_PHYSICAL_CPUS > 32
-#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
-#else
-#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
-#endif
+#define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
static inline void set_bios_reset(void)
{
diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c
index 16c56a2c83..a00fc15653 100644
--- a/src/southbridge/amd/cimx/sb800/reset.c
+++ b/src/southbridge/amd/cimx/sb800/reset.c
@@ -26,11 +26,7 @@
#define HT_INIT_CONTROL 0x6C
#define HTIC_BIOSR_Detect (1<<5)
-#if CONFIG_MAX_PHYSICAL_CPUS > 32
-#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
-#else
-#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
-#endif
+#define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
static inline void set_bios_reset(void)
{
diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c
index 16c56a2c83..a00fc15653 100644
--- a/src/southbridge/amd/cimx/sb900/reset.c
+++ b/src/southbridge/amd/cimx/sb900/reset.c
@@ -26,11 +26,7 @@
#define HT_INIT_CONTROL 0x6C
#define HTIC_BIOSR_Detect (1<<5)
-#if CONFIG_MAX_PHYSICAL_CPUS > 32
-#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
-#else
-#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
-#endif
+#define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
static inline void set_bios_reset(void)
{